COM20019I3V-DZD SMSC, COM20019I3V-DZD Datasheet - Page 9

• Manufacturer Part Number: COM20019I3V-DZD
• Description: Network Controller & Processor ICs ARCNET Contrllr
• Manufacturer: SMSC

Specifications of COM20019I3V-DZD

• Product: Controller Area Network (CAN)
• Number Of Transceivers: 1
• Data Rate: 312.5 Kbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Supply Current (max): 25 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SMSC COM20019I 3.3V Rev.C
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
4, 5, 6,
10, 11,
PLCC
1, 2,
8, 9,
12
26
27
23
24
25
3
-
PIN NO
7, 9, 10,
Chapter 3
44, 45,
1, 2, 4,
12, 13
TQFP
46
37
39
31
34
36
26
Address
0-2
Data 0-7
nWrite/
Direction
nRead/
nData
Strobe
nReset In
nInterrupt
nChip
Select
Read/Write
Bus Timing
Select
NAME
A0/nMUX
A1
A2/ALE
AD0-AD2,
D3-D7
nWR/DIR
nRD/nDS
nRESET
nINTR
nCS
BUSTMG
SYMBOL
Description of Pin Functions
DATASHEET
MICROCONTROLLER INTERFACE
OUT
I/O
I/O
IN
IN
IN
IN
IN
IN
IN
IN
Page 9
On a non-multiplexed mode, A0-A2 are address
input bits. (A0 is the LSB) On a multiplexed
address/data bus, nMUX tied Low, A1 is left open,
and ALE is tied to the Address Latch Enable signal.
A1 is connected to an internal pull-up resistor.
On a non-multiplexed bus, these signals are used
as the lower byte data bus lines. On a multiplexed
address/data bus, AD0-AD2 act as the address
lines (latched by ALE) and as the low data lines.
D3-D7 are always used for data only. These signals
are connected to internal pull-up resistors.
nWR is for 80xx CPU, nWR is Write signal input.
Active Low.
DIR is for 68xx CPU, DIR is Bus Direction signal
input. (Low: Write, High: Read.)
nRD is for 80xx CPU, nRD is Read signal input.
Active Low.
nDS is for 68xx CPU, nDS is Data Strobe signal
input. Active Low.
Hardware reset signal. Active Low.
Interrupt signal output. Active Low.
Chip Select input. Active Low.
Read and Write Bus Access Timing mode selecting
signal. Status of this signal effects CPU Timing.
L: High speed timing mode (only for non-
H: Normal timing mode
This signal is connected to internal pull-up registers.
NOTE:
BUSTMG pin does not exist in PLCC package.
multiplexed bus)
DESCRIPTION
Rev. 11-07-08