COM20020I3V-HT SMSC, COM20020I3V-HT Datasheet - Page 26

• Manufacturer Part Number: COM20020I3V-HT
• Description: Network Controller & Processor ICs ARCNET Contrllr
• Manufacturer: SMSC

Specifications of COM20020I3V-HT

• Product: Controller Area Network (CAN)
• Number Of Transceivers: 1
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 35 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
interaction with the network. The node determines the existence of other nodes by placing a Node ID value in the
Tentative ID Register and waiting to see if the Tentative ID bit of the Diagnostic Status Register gets set. The network map
developed by this method is only valid for a short period of time, since nodes may join or depart from the network at any
time. When using the Tentative ID feature, a node cannot detect the existence of the next logical node to which it
passes the token. The Next ID Register will hold the ID value of that node. The Tentative ID Register defaults to the
value 0000 0000 upon hardware reset only.
Node ID Register
The Node ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up accordingly (please
refer to the Configuration Register and SUB ADR Register). The Node ID Register contains the unique value which
identifies this particular node. Each node on the network must have a unique Node ID value at all times. The Duplicate
ID bit of the Diagnostic Status Register helps the user find a unique Node ID. Refer to the Initialization Sequence section
for further detail on the use of the DUPID bit. The core of the COM20020I 3V does not wake up until a Node ID other
than zero is written into the Node ID Register. During this time, no microcode is executed, no tokens are passed by this
node, and no reconfigurations are caused by this node. Once a non-zero NodeID is placed into the Node ID Register,
the core wakes up but will not join the network until the TXEN bit of the Configuration Register is set. While the
Transmitter is disabled, the Receiver portion of the device is still functional and will provide the user with useful
information about the network. The Node ID Register defaults to the value 0000 0000 upon hardware reset only.
Next ID Register
The Next ID Register is an 8-bit, read-only register, accessed when the sub-address bits are set up accordingly (please
refer to the Configuration Register and SUB ADR Register). The Next ID Register holds the value of the Node ID to which
the COM20020I 3V will pass the token. When used in conjunction with the Tentative ID Register, the Next ID Register
can provide a complete network map. The Next ID Register is updated each time a node enters/leaves the network or
when a network reconfiguration occurs. Each time the microsequencer updates the Next ID Register, a New Next ID
interrupt is generated. This bit is cleared by reading the Next ID Register. Default value is 0000 0000 upon hardware or
software reset.
Status Register
The COM20020I 3V Status Register is an 8-bit read-only register. All of the bits, except for bits 5 and 6, are software
compatible with previous SMSC ARCNET devices. In previous SMSC ARCNET devices the Extended Timeout status
was provided in bits 5 and 6 of the Status Register. In the COM20020I 3V, the COM20020, the COM90C66, and the
COM90C165, COM20020-5, COM20051 and COM20051+ these bits exist in and are controlled by the Configuration
Register. The Status Register contents are defined as in Table 4, but are defined differently during the Command
Chaining operation. Please refer to the Command Chaining section for the definition of the Status Register during
Command Chaining operation. The Status Register defaults to the value 1XX1 0001 upon either hardware or software
reset.
Diagnostic Status Register
The Diagnostic Status Register contains seven read-only bits which help the user troubleshoot the network or node
operation. Various combinations of these bits and the TXEN bit of the Configuration Register represent different situations.
All of these bits, except the Excessive NAcK bit and the New Next ID bit, are reset to logic "0" upon reading the
Diagnostic Status Register or upon software or hardware reset. The EXCNAK bit is reset by the "POR Clear Flags"
command or upon software or hardware reset. The Diagnostic Status Register defaults to the value 0000 000X upon
either hardware or software reset.
Command Register
Execution of commands are initiated by performing microcontroller writes to this register. Any combinations of written
data other than those listed in Table 5 are not permitted and may result in incorrect chip and/or network operation.
Address Pointer Registers
These read/write registers are each 8-bits wide and are used for addressing the internal RAM. New pointer addresses
should be written by first writing to the High Register and then writing to the Low Register because writing to the Low
Register loads the address. The contents of the Address Pointer High and Low Registers are undefined upon hardware
reset. Writing to Address Pointer low loads the address.
Configuration Register
The Configuration Register is a read/write register which is used to configure the different modes of the COM20020I 3V.
The Configuration Register defaults to the value 0001 1000 upon hardware reset only. SUBAD0 and SUBAD1 point to the
selection in Register 7.
Sub-Address Register
SMSC COM20020I 3.3V Rev.E
Page 26
Revision 09-11-06
DATASHEET