ISPGDX120A-7T176 Lattice, ISPGDX120A-7T176 Datasheet - Page 9

• Manufacturer Part Number: ISPGDX120A-7T176
• Description: Analog & Digital Crosspoint ICs PROGRAMMABLE GEN DIG CROSSPOINT
• Manufacturer: Lattice

Specifications of ISPGDX120A-7T176

• Mounting Style: Through Hole
• Number Of Arrays: 1
• Operating Supply Voltage: 5 V
• Supply Type: Single
• Configuration: 120 x 120
• Package / Case: DIP-24
• Input Level: TTL
• Output Level: TTL
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. All timings measured with one output switching, fast output slew rate setting, except
ispGDX timings are specified with a GRP load (fanout) of
four I/O cells. The figure at right shows the Maximum ∆
GRP Delay with increased GRP loads. These deltas
apply to any signal path traversing the GRP (MUXA-D,
OE, CLK, MUXsel0-1). Global Clock signals, which do
not use the GRP, have no fanout delay adder.
PARAMETER
External Timing Parameters
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
pd
sel
max(ext)
su1
su2
h
gco1
gco2
co1
co2
en
dis
toeen
toedis
wh
wl
rst
rw
sl
sk
COND.
TEST
C
C
A
A
A
A
A
A
B
B
A
A
–
–
–
–
–
–
–
–
1
10
11
12
13
14
15
16
17
18
19
20
#
1
2
3
4
5
6
7
8
9
Data Propagation Delay from any I/O pin to any I/O pin
Data Propagation Delay from MUXsel Inputs to any Output
Clock Frequency with External Feedback
Input Latch or Register Setup Time before any Clk
Output Latch or Register MUX Data Setup Time before any Clk
Latch or Register Hold Time after any Clk
Output Latch or Register Clk (from Y
Input Latch or Register Clk (from Y
Output Latch or Register Clk (from I/O pin) to Output Delay
Input Latch or Register Clock (from I/O pin) to Output Delay
Input to Output Enable
Input to Output Disable
Test OE Output Enable
Test OE Output Disable
Clock Pulse Duration, High
Clock Pulse Duration, Low
Register Reset Delay from RESET Low
Reset pulse width
Output Delay Adder for Output Timings Using Slow Slew Rate
Output Skew (tgco1 across chip)
Over Recommended Operating Conditions
DESCRIPTION
x
8
) to Output Delay
x
Specifications ispGDX Family
) to Output Delay
(
tsu2+tgco1
10
8
6
4
2
1
0
Maximum
4
)
10
t
sl
.
20
∆
GRP Delay vs. I/O Cell Fanout
I/O Cell Fanout
MIN. MAX.
10.0
111
4.0
4.0
0.0
3.5
3.5
–
–
–
–
–
–
–
–
–
–
–
–
30
-5
14.0
5.0
6.5
8.5
6.0
9.5
6.0
6.0
9.0
9.0
5.0
0.5
–
–
–
–
5
–
–
–
40
MIN. MAX.
80.0
14.0
5.5
5.5
0.0
5.0
5.0
–
–
–
–
–
–
–
–
–
–
–
–
50
-7
11.0
13.0
12.0
12.0
18.0
7.0
9.0
7.0
9.0
8.5
8.5
7.0
0.5
60
–
–
–
–
–
–
–
UNITS
MHz
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns