CS61584A-IQ5 Cirrus Logic Inc, CS61584A-IQ5 Datasheet - Page 30

• Manufacturer Part Number: CS61584A-IQ5
• Description: Network Controller & Processor ICs IC 3.3V/5V Dual T1/ E1 Line Intrfc Unit
• Manufacturer: Cirrus Logic Inc

Specifications of CS61584A-IQ5

• Product: Framer
• Number Of Transceivers: 2
• Data Rate: 2.048 Mbps
• Supply Voltage (max): 3.465 V, 5.25 V
• Supply Voltage (min): 3.135 V, 4.75 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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9.2
Serial port operation in Host mode is selected when
the MODE pin is set high and the P/S pin is set low.
In this mode, the CS61584A register set is accessed
by setting the chip select (CS) pin low and commu-
nicating over the SDI, SDO, and SCLK pins. Tim-
ing over the serial port is independent of the
transmit and receive system timing. Figure 21 illus-
trates the format of serial port data transfers.
A read or write is initiated by writing an ad-
dress/command byte (ACB) to SDI. During a read
cycle, the register data addressed by the ACB is
output on SDO on the next eight SCLK clock cy-
cles. During a write cycle, the data byte immediate-
ly follows the ACB. A second address byte is
required when reading or writing the Arbitrary
Waveform registers (see below).
Data is written to and read from the serial port in
LSB first format. When writing to the port, SDI in-
put data is sampled by the device on the rising edge
of SCLK. The polarity of the data output on SDO is
controlled by the SPOL pin. When the SPOL pin is
low, data on SDO is valid on the rising edge of
SCLK. When the SPOL pin is high, data on SDO is
valid on the falling edge of SCLK. The SDO pin is
30
SDO
CS
SCLK
SDI
B7 (MSB)
Reserved
0
Serial Port Operation
R/W
Reserved
B6
0
0
Address/Command Byte(s)
0
Figure 21. Serial Read/Write Format (SPOL = 0)
ADR4
MSB
B5
0
Figure 22. Address Command byte
0
ADR3
1
B4
DS261PP5
0
Address Field
high impedance when not transmitting data. If the
host processor has a bi-directional I/O port, SDI
and SDO may be tied together.
As illustrated in Figure 22, the ACB consists of a
R/W bit, address field, and two reserved bits. The
R/W bit specifies if the current register access is a
read (R/W = 1) or a write (R/W = 0) operation. The
address field specifies the register address from
0x10 to 0x19. The reserved bit must be cleared for
normal operation of serial mode.
During register addressing, the first eight registers
are addressed as 0x10 to 0x17 in the address field
of the ACB. Because Arbitrary Waveform registers
0x18 and 0x19 access multiple bytes of RAM,
reading or writing these registers requires an Ad-
dress Command Byte followed by a RAM address
byte for each data transfer. The ACB specifies ei-
ther 0x18 or 0x19 in the address field to access the
channel 1 or channel 2 Arbitrary Waveform regis-
ter set. The RAM address is an 8-bit, unsigned bi-
nary number in the range of 0x00 to 0x29 to
identify one of 42 RAM locations. The data byte
containing the 7-bit, 2’s complement number spec-
ifying the phase amplitude completes the 24 SCLK
write cycle.
0
ADR2
B3
D0
D0
D1
D1
ADR1
B2
D2
D2
Data Output
Data Input
D3
D3
D4
D4
ADR0
LSB
B1
D5
D5
CS61584A
CS61584A
D6
D6
0 = Write
1 = Read
DS261PP5
R/W
DS261F1
B0
D7
D7