MT88E46AS Zarlink, MT88E46AS Datasheet - Page 10

• Manufacturer Part Number: MT88E46AS
• Description: Caller ID CMOS 3.58MHz 3.3V/5V 20-Pin SOIC Tube
• Manufacturer: Zarlink

Specifications of MT88E46AS

• Package: 20SOIC
• Telecommunication Standards Supported: Bellcore GR-30-CORE|SR-TSV-002476|TIA/EIA-716|TIA/EIA-777
• Fabrication Technology: CMOS
• Maximum Data Rate: 1.212 KBd
• Typical Operating Supply Voltage: 3.3|5 V
• Typical Supply Current: 4.3 mA
• Minimum Operating Temperature: -40 °C
• Maximum Operating Temperature: 85 °C
• Operating Frequency: 3.58 MHz

MT88E46
10
byte DR goes low to indicate that a new byte has become
available. The microcontroller applies pulses at the DCLK
input pin to read the register contents serially out of the
DATA pin (see Figure 15).
Internal to the MT88E46, the start bit is stripped off, the
data bits and the trailing stop bit are sampled and stored.
Midway through the stop bit, the 8 data bits and the stop
bit are parallel loaded into a 9 bit shift register and DR
goes low. The register’s contents are shifted out to the
DATA pin on the supplied DCLK’s rising edges in the
order they were received. The last bit must be shifted out
and DCLK returned to low before the next DR. DCLK
must be low for t
for t
Electrical Characteristics - Mode 1 FSK Data Interface
Timing’).
If DCLK begins while DR is low, DR will return to high
upon the first DCLK rising edge. If DR interrupts a
microcontroller then this feature allows the interrupt to be
cleared by the first read pulse. Otherwise DR is low for
half a nominal bit time (1/2400 sec).
Reading the stop bit allows the software to check for
framing errors. When framing error is not checked the
microcontroller only needs to send 8 DCLK pulses to shift
the data byte out.
FSK Carrier Detector
The carrier detector provides an indication of the presence
of a signal in the FSK frequency band. It detects the
presence of a signal of sufficient amplitude at the output
of the FSK bandpass filter.
The signal is qualified by a digital algorithm before the
CD output is set low to indicate carrier detection. A 10 ms
hysteresis has been provided to allow for momentary
signal dropout once CD has been activated. CD is released
when there is no activity at the FSK bandpass filter output
for 10ms.
When CD is inactive (high), the raw output of the FSK
demodulator is ignored by the internal data timing
recovery circuit. In FSK interface mode 0 the DATA,
DCLK and DR outputs are forced high. In mode 1 the
output shift register is not updated and DR is high; if
DCLK is clocked, DATA is undefined.
Note that signals such as speech, CAS and DTMF tones
also lie in the FSK frequency band and the carrier detector
may be activated by these signals. They will be
demodulated and presented as data. To avoid the false
data, the MT88E46 should be put into CAS or power
down mode when FSK is not expected. Ringing, on the
other hand, does not pose a problem as it is ignored by the
carrier detector.
DDH
after DR has gone low (see Figure 15 and ‘AC
DDS
before DR goes low and remain low
Interrupt
The DR/DET output can be used to interrupt a
microcontroller. When the MT88E46 is the only interrupt
source, DR/DET can be connected directly to the
microcontroller’s interrupt input. Figure 7 shows the
necessary connections when the MT88E46 is one of many
interrupt sources. The diodes and resistors implement a
wired-or so that the microcontroller is interrupted (INT
low active or falling edge triggered) when one or more of
INT1, INT2 or DR/DET is low. The microcontroller can
determine which one of DR/DET
the interrupt by reading them into an input port.
Power Down
The MT88E46 can be powered down to consume virtually
no power supply current via a state of the CB0/1/2 pins.
Momentary transition of CB0/1/2 into the power down
code will not activate power down. In power down mode
both input op-amps, V
operational; DCLK becomes an input pin because to
select the power down state CB0 is 1 which selects FSK
interface mode 1. If the application uses FSK interface
mode 0 and the MT88E46 needs to be powered down,
then during power down the input state of the DCLK input
must be defined, for example, by a pull down resistor
(R13 in Figure 8) so that the MT88E46 will draw minimal
power supply current. When the MT88E46 is powered
down DATA, DR/DET, CD are high.
To reduce the operating current a partial power down
feature has been incorporated. When FSK is selected, the
CAS detector is powered down. When CAS is selected the
FSK demodulator is powered down. The two input op-
amps are not affected and both will remain operational.
The partial power down feature can also be used to reset
the FSK or CAS circuits, such as upon system power up.
To reset the FSK demodulator, use CB1/2 to select CAS
mode for about 10 µs, DR will become high. To reset the
CAS detector, select FSK mode for about 10µs, DET will
become high.
Oscillator
The MT88E46 requires a 3.579545MHz crystal to
generate its oscillator clock. To meet the CAS detection
frequency tolerance specifications the crystal must have a
0.1% frequency tolerance. The crystal specification is as
follows:
Frequency:
Frequency Tolerance:
REF
and the oscillator are not
,
3.579545 MHz
±0.1% (over
temperature range
of the application)
INT1
or
Data Sheet
INT2 caused