MT8964AE1 Zarlink, MT8964AE1 Datasheet - Page 9

• Manufacturer Part Number: MT8964AE1
• Description: Audio Codec 1ADC / 1DAC 8-Bit 18-Pin PDIP Tube
• Manufacturer: Zarlink
• Type: PCMr

Specifications of MT8964AE1

• Package: 18PDIP
• Adc/dac Resolution: 8 Bit
• Number Of Channels: 1ADC /1 DAC
• Number Of Adc Inputs: 2
• Number Of Dacs: 1
• Operating Supply Voltage: ±5 V

Control Registers A, B
The contents of these registers control the filter/codec functions as described in Tables 2 and 3.
Bit 7 of the registers is the MSB and is defined as the first bit of the serial data stream input (corresponding to the
sign bit of the PCM word).
On initial power-up these registers are set to the powerdown condition for a maximum of 25 clock cycles. During
this time it is impossible to change the data in these registers.
Chip Testing
By enabling Register B with valid data (eight-bit control word input to CSTi when F1i=GNDD and CA= V
testing mode can be entered. Bits 6 and 7 (most sign bits) define states for testing the transmit filter, receive filter
and the codec function. The input in each case is V
details.)
Loopback
Loopback of the filter/codec is controlled by the control word entered into Register A. Bits 6 and 7 (most sign bits)
provide either a digital or analog loopback condition. Digital loopback is defined as follows:
•
•
•
Analog loopback is defined as follows:
•
•
•
•
In both cases of loopback, DSTi is the input and DSTo is the output.
PCM input data at DSTi is latched into the PCM input register and the output of this register is connected to
the input of the 3-state PCM output register.
The digital input to the PCM digital-to-analog decoder is disconnected, forced to zero (0).
The output of the PCM encoder is disabled and thus the encoded data is lost. The PCM output at DSTo is
determined by the PCM input data.
PCM input data is latched, decoded and filtered as normal but not output at V
Analog output buffer at V
Analog input at V
The receive filter output is connected to the transmit filter input. Thus the decode signal is fed back through
the receive path and encoded in the normal way. The analog output buffer at V
configuration.
X
is disconnected from the transmit filter input.
R
has its input shorted to GNDA and disconnected from the receive filter output.
BIT 2
BIT 7
0
0
1
1
MT8960/61/62/63/64/65/66/67
Table 2 - Control States - Register A
BIT 1
BIT 6
0
1
0
1
Zarlink Semiconductor Inc.
X
input and the output in each case is V
BIT 0
FUNCTION CONTROL
9
Normal operation
Analog Loopback
Digital Loopback
Powerdown
FILTER GAIN (dB)
TRANSMIT (A/D)
R
.
R
is not tested by this
R
output. (See Table 3 for
Data Sheet
CC
) the chip