AT84CS001VTPY E2V, AT84CS001VTPY Datasheet - Page 20

• Manufacturer Part Number: AT84CS001VTPY
• Description: Demultiplexer 240-Pin EBGA
• Manufacturer: E2V

Specifications of AT84CS001VTPY

• Package: 240EBGA
• Power Supply Type: Analog|Digital
• Typical Supply Current: 600 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 2.375|3.15 V
• Maximum Operating Supply Voltage: 2.625|3.45 V

Figure 4-1.
20
ASYNCRST
CLK
CLK
CLK
CLK
0809E–BDC–05/09
CLK to ASYNCRST Timing with V(CLKDACTRL) = V
Not allowed in CLK/2 mode
Not allowed
Allowed
Allowed (recommended)
Allowed in CLK mode
It is highly recommended to stop the clock at the Low level when ASYNCRST is active (high level). Note
that when e2v's ADCs are in reset, the ADC Data Ready output (input clock of the DMUX) is stopped at
the low level. In the case where the clock can not be stopped during the reset (not recommended), it is
not allowed to have an active edge (rising edge in CLK mode but both rising and falling edge in CLK/2
mode) of the CLK clock within a ±125 ps area around the falling edge of ASYNCRST.
The end of the reset occurs at the falling edge of ASYNCRST, and the active edge of the Clock has to
occur at the minimum 125 ps after the falling edge of ASYNCRST to ensure a proper timing.
The figure represented above is given for V(CLKDACTRL) = V
ferent value, the forbidden area has to be shifted accordingly to V(CLKDACTRL) value. Please refer to
Figure 3-11 on page 12
For example, assuming ambient temperature and typical supplies, if V(CLKDACTRL) is set to 2.2V, the
additional delay compared to 1.65V is 2.55 ns - 2.25 ns = 300 ps. This means that it is forbidden to have
an active edge of the clock within - 425 ps/- 175 ps (the forbidden area is shifted on the left on the above
figure).
ALLOWED
1 ns min
for delay calculation.
125 ps
FORBIDDEN
125 ps
CC
/2g
CC
/2 = 1.65V. If V(CLKDACTRL) has a dif-
ALLOWED
e2v semiconductors SAS 2009
AT84CS001