AD7722ASZ Analog Devices Inc, AD7722ASZ Datasheet - Page 8

• Manufacturer Part Number: AD7722ASZ
• Description: ADC Single Delta-Sigma 195KSPS 16-Bit Parallel/Serial 44-Pin MQFP
• Manufacturer: Analog Devices Inc

Specifications of AD7722ASZ

• Package: 44MQFP
• Resolution: 16 Bit
• Sampling Rate: 195 KSPS
• Architecture: Delta-Sigma
• Number Of Analog Inputs: 1
• Digital Interface Type: Parallel|Serial (3-Wire)
• Input Type: Voltage
• Polarity Of Input Voltage: Unipolar|Bipolar
• Number Of Bits: 16
• Sampling Rate (per Second): 220k
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 375mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7722
Mnemonic
AV
AGND1
AV
AGND
DV
DGND
REF1
REF2
V
V
UNI
CLKIN
XTAL
P/S
CAL
RESET
CS
SYNC
IN
IN
DD1
DD
DD
(+)
(–)
Pin No.
14
10
20, 23
9, 13, 15, 19, Ground Reference for Analog Circuitry.
21, 25, 26
39
6, 28
22
24
18
16
7
11
12
8
27
17
29
30
Description
Clock Logic Power Supply Voltage for the Analog Modulator, 5 V ± 5%.
Clock Logic Ground Reference for the Analog Modulator.
Analog Power Supply Voltage, 5 V ± 5%.
Digital Power Supply Voltage, 5 V ± 5%.
Ground Reference for Digital Circuitry.
Reference Input/Output. REF1 connects through 3 kΩ to the output of the internal 2.5 V reference and
to the input of a buffer amplifier that drives the Σ-∆ modulator. This pin can also be overdriven with an
external reference 2.5 V.
Reference Input/Output. REF2 connects to the output of an internal buffer amplifier used to drive the
Σ-∆ modulator. When REF2 is used as an input, REF1 must be connected to AGND.
Positive Terminal of the Differential Analog Input.
Negative Terminal of the Differential Analog Input.
Analog Input Range Select Input. UNI selects the analog input range for either bipolar or unipolar
operation. A logic low input selects unipolar operation. A logic high input selects bipolar operation.
Clock Input. Master clock signal for the device. The CLKIN pin interfaces the AD7722 internal
oscillator circuit to an external crystal or an external clock. A parallel resonant, fundamental-frequency,
microprocessor-grade crystal and a 1 MΩ resistor should be connected between the CLKIN and
XTAL pins with two capacitors connected from each pin to ground. Alternatively, the CLKIN pin
can be driven with an external CMOS compatible clock. The AD7722 is specified with a clock input
frequency of 12.5 MHz.
Oscillator Output. The XTAL pin connects the internal oscillator output to an external crystal.
If an external clock is used, XTAL should be left unconnected.
Parallel/Serial Interface Select Input. A logic high configures the output data interface for parallel mode
operation. The serial mode operation is selected with the P/S set to a logic low.
Calibration Logic Input. A logic high input for a duration of one CLKIN cycle initiates a
calibration sequence for the device gain and offset error.
Reset Logic Input. RESET is used to clear the offset and gain calibration registers. RESET is an
asynchronous input. RESET allows the user to set the AD7722 to an uncalibrated state if the
device had been previously calibrated. A rising edge also resets the AD7722 Σ-∆ modulator by
shorting the integrator capacitors in the modulator. In addition, RESET functions identically to
the SYNC pin described below. When operating with more than one AD7722, a RESET/SYNC
should be issued following power up to ensure the devices are synchronized. Ensure that the
supplies are settled before applying the RESET/SYNC pulse.
Chip select is a level sensitive logic input. CS enables the output data register for parallel mode read
operation. The CS logic level is sensed on the rising edge of CLKIN. The output data bus is enabled
when the rising edge of CLKIN senses a logic low level on CS if RD is also low. When CS is sensed
high, the output data bits DB15–DB0 will be high impedance. In serial mode, tie CS to a logic low.
Synchronization Logic Input. SYNC is an asynchronous input. When using more than one
AD7722 operated from a common master clock, SYNC allows each ADC’s Σ-∆ modulator to
simultaneously sample its analog input and update its output data register. A rising edge resets
the AD7722 digital filter sequencer counter to zero. After a SYNC, conversion data is not valid until
after the digital filter settles (see Figure 7). DVAL goes low in the serial mode. When the rising
edge of CLKIN senses a logic low on SYNC (or RESET), the reset state is released; in parallel
mode, DRDY goes high. After the reset state is released, DVAL returns high after 8192 CLKIN
cycles (128 × 64/f
of the digital filter (64 CLKIN periods), when valid data is ready to be read from the output data
register. When operating with more than one AD7722, a RESET/SYNC should be issued follow-
ing power up to ensure the devices are synchronized. Ensure that the supplies are settled before
applying the RESET/SYNC pulse.
PIN FUNCTION DESCRIPTIONS
CLKIN
); in parallel mode, DRDY returns low after one additional convolution cycle
–8–
REV. B