AD7398BRU Analog Devices Inc, AD7398BRU Datasheet - Page 7

• Manufacturer Part Number: AD7398BRU
• Description: DAC 4-CH R-2R 12-Bit 16-Pin TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7398BRU

• Package: 16TSSOP
• Resolution: 12 Bit
• Conversion Rate: 167 KSPS
• Architecture: R-2R
• Digital Interface Type: Serial (3-Wire, SPI)
• Number Of Outputs Per Chip: 4
• Output Type: Voltage
• Full Scale Error: ±2.5 mV
• Integral Nonlinearity Error: ±1.5 LSB
• Maximum Settling Time: 6(Typ) us
• Rohs Status: RoHS non-compliant
• Settling Time: 6µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 16mW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Table 5. Control Logic Truth Table
CS
H
L
L
L
↑+
H
H
NOTES
1. ↑+ = Positive logic transition; ↓– = Negative logic transition; X = Don’t Care.
2. At power-on, both the input register and the DAC register are loaded with all zeros.
3. During power shutdown, reprogramming of any internal registers can take place, but the output amplifiers do not produce the new values until the part is taken out
4. The LDAC input is a level-sensitive input that controls the four DAC registers.
of shutdown mode.
CLK
X
L
↑+
H
L/H
X
X
Mnemonic
V
V
V
V
V
GND
LDAC
RS
CS
CLK
SDI
V
V
V
V
V
OUT
OUT
SS
REF
REF
REF
REF
DD
OUT
OUT
A
B
D
C
B
A
D
C
LDAC
H
H
H
H
H
L
↑+
Description
DAC B Voltage Output.
DAC A Voltage Output.
Negative Power Supply Input. Specified range of operation 0 V to −5.5 V.
DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can be tied to V
DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can be tied to V
Ground Pin.
Load DAC Register Strobe. Level sensitive active low. Transfers all input register data to DAC registers.
Resets Input and DAC Registers to All Zero Codes. Shift register contents unchanged.
Chip Select. Active low input. Disables shift register loading when high. Transfers serial register data to the input
Schmitt Triggered Clock Input. Positive edge clocks data into shift register.
Serial Data Input. Input data loads directly into the shift register.
DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can be tied to V
DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can be tied to V
Positive Power Supply Input. Specified range of operation 3 V to 5 V ± 10%.
DAC D Voltage Output.
DAC C Voltage Output.
Asynchronous active low input. See Table 5 for operation.
register when CS returns high. Does not effect LDAC operation.
Serial Shift Register Function
No effect
No effect
Shift register data advanced one bit
No effect
No effect
No effect
No effect
V
V
V
V
LDAC
OUT
OUT
REF
REF
GND
V
RS
SS
Figure 5. Pin Configuration
B
A
A
B
1
2
3
4
5
6
7
8
Rev. C | Page 7 of 24
(Not to Scale)
AD7398/
AD7399
TOP VIEW
Input Register Function
No effect
No effect
Latched
Latched
Updated with shift register contents
Latched
Latched
16
15
14
13
12
11
10
9
V
V
V
V
V
SDI
CLK
CS
OUT
OUT
DD
REF
REF
C
D
C
D
AD7398/AD7399
DAC Register
No effect
No effect
No effect
No effect
No effect
Transparent
Latched
DD
DD
DD
DD
pin or V
pin or V
pin or V
pin or V
SS
SS
SS
SS
pin.
pin.
pin.
pin.