74LVC138APW-T NXP Semiconductors, 74LVC138APW-T Datasheet - Page 2

• Manufacturer Part Number: 74LVC138APW-T
• Description: Decoder/Demultiplexer Single 3-to-8 16-Pin TSSOP T/R
• Manufacturer: NXP Semiconductors

Specifications of 74LVC138APW-T

• Package: 16TSSOP
• Logic Function: Decoder/Demultiplexer
• Logic Family: LVC
• Number Of Element Outputs: 8
• Number Of Elements Per Chip: 1
• Number Of Input Enables Per Element: 3
• Demultiplexing Capability: 1-of-8
• Fabrication Technology: CMOS
• Tolerant I/os: 5 Inputs V
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Operating Temperature: -40 to 125 °C

Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. The condition is V
2003 May 06
t
C
C
PHL
SYMBOL
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Active LOW mutually exclusive outputs
Output drive capability 50
125 C
Complies with JEDEC standard no. 8-1A
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from 40 to +85 C and 40 to +125 C.
I
PD
3-to-8 line decoder/demultiplexer; inverting
P
f
f
C
V
N = total switching outputs;
i
o
/t
(C
D
CC
PD
= input frequency in MHz;
L
PLH
= output frequency in MHz;
= output load capacitance in pF;
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in Volts;
PD
V
CC
amb
propagation delay An to Yn
propagation delay E3 to Yn
propagation delay En to Yn
input capacitance
power dissipation capacitance per gate
2
V
CC
= 25 C; t
f
o
2
) = sum of the outputs.
I
f
= GND to V
i
N + (C
r
= t
PARAMETER
transmission lines at
f
2.5 ns.
L
CC
.
V
CC
2
f
o
) where:
2
C
C
C
V
CC
L
L
L
DESCRIPTION
The 74LVC138A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
The 74LVC138A accepts three binary weighted address
inputs (A0, A1 and A2) and when enabled, provides 8
mutually exclusive active LOW outputs (Y0 to Y7).
The 74LVC138A features three enable inputs: two active
LOW (E1 and E2) and one active HIGH (E3). Every output
will be HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel
expansion of the 74LVC138A to a 1-of-32 (5 to 32 lines)
decoder with just four 74LVC138A ICs and one inverter.
The 74LVC138A can be used as an eight output
demultiplexer by using one of the active LOW enable
inputs as the data input and the remaining enable inputs as
strobes. Unused enable inputs must be permanently tied
to their appropriate active HIGH or LOW state.
= 50 pF; V
= 50 pF; V
= 50 pF; V
D
= 3.3 V; notes 1 and 2
in W).
CONDITIONS
CC
CC
CC
= 3.3 V
= 3.3 V
= 3.3 V
2.6
2.8
2.7
4.0
21
TYPICAL
Product specification
74LVC138A
ns
ns
ns
pF
pF
UNIT