M4A5-128/64-10VC LATTICE SEMICONDUCTOR, M4A5-128/64-10VC Datasheet - Page 19

• Manufacturer Part Number: M4A5-128/64-10VC
• Description: CPLD ispMACH™ 4A Family 5K Gates 128 Macro Cells 83.3MHz/118MHz EECMOS Technology 5V 100-Pin TQFP Tray
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of M4A5-128/64-10VC

• Package: 100TQFP
• Family Name: ispMACH™ 4A
• Device System Gates: 5000
• Number Of Macro Cells: 128
• Maximum Propagation Delay Time: 10 ns
• Number Of User I/os: 64
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 83.3|118 MHz
• Number Of Product Terms Per Macro: 20
• Operating Temperature: 0 to 70 °C

PAL Block Clock Generation
Each ispMACH 4A device has four clock pins that can also be used as inputs. These pins drive a clock
generator in each PAL block (Figure 14). The clock generator provides four clock signals that can be used
anywhere in the PAL block. These four PAL block clock signals can consist of a large number of
combinations of the true and complement edges of the global clock signals. Table 14 lists the possible
combinations.
1. M4A(3,5)-32/32 and M4A(3,5)-64/32 have only two clock pins, GCLK0 and GCLK1. GCLK2 is tied to GCLK0, and GCLK3 is tied to GCLK1.
Note:
1. Values in parentheses are for the M4A(3,5)-32/32 and M4A(3,5)-64/32.
This feature provides high flexibility for partitioning state machines and dual-phase clocks. It also allows
latches to be driven with either polarity of latch enable, and in a master-slave configuration.
Block CLK0
GCLK0
GCLK1
GCLK0
GCLK1
X
X
X
X
GCLK2
GCLK3
GCLK1
GCLK0
Table 14. PAL Block Clock Combinations
Figure 14. PAL Block Clock Generator
Block CLK1
GCLK1
GCLK1
GCLK0
GCLK0
X
X
X
X
ispMACH 4A Family
Block CLK2
(GCLK2 or GCLK3)
Block CLK0
(GCLK0 or GCLK1)
Block CLK1
(GCLK1 or GCLK0)
Block CLK3
(GCLK3 or GCLK2)
GCLK2 (GCLK0)
GCLK3 (GCLK1)
GCLK2 (GCLK0)
GCLK3 (GCLK1)
Block CLK2
X
X
X
X
1
1
GCLK3 (GCLK1)
GCLK3 (GCLK1)
GCLK2 (GCLK0)
GCLK2 (GCLK0)
Block CLK3
X
X
X
X
17466G-004
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