XC2C256-7FT256I Xilinx Inc, XC2C256-7FT256I Datasheet - Page 10

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XC2C256-7FT256I

Manufacturer Part Number
XC2C256-7FT256I
Description
CPLD CoolRunner™-II Family 6K Gates 256 Macro Cells 152MHz 0.18um (CMOS) Technology 1.8V 256-Pin FTBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2C256-7FT256I

Package
256FTBGA
Family Name
CoolRunner™-II
Device System Gates
6000
Maximum Propagation Delay Time
7.5 ns
Number Of User I/os
184
Number Of Logic Blocks/elements
16
Typical Operating Supply Voltage
1.8 V
Maximum Operating Frequency
152 MHz
Number Of Product Terms Per Macro
40
Operating Temperature
-40 to 85 °C

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CoolRunner-II CPLD Family
Design Security
Designs can be secured during programming to prevent
either accidental overwriting or pattern theft via readback.
Four independent levels of security are provided on-chip,
10
Figure 10: CoolCLOCK Created by Cascading Clock Divider and DualEDGE Option
Figure 9: Macrocell Clock Chain with DualEDGE Option Shown
Synch Reset
CLK_CT
PTC
GCK2
CTC
PTC
GCK0
GCK1
GCK2
GCK0
GCK1
GCK2
www.xilinx.com
Clock
In
Synch Rst
eliminating any electrical or visual detection of configuration
patterns. These security bits can be reset only by erasing
the entire device. See
÷10
÷12
÷14
÷16
÷2
÷4
÷6
÷8
PTC
PTC
D/T
CE
CK
D/T
CE
CK
DS090_09_121201
FIF
Latch
DualEDGE
FIF
Latch
DualEDGE
WP170
Q
DS090 (v3.1) September 11, 2008
Q
for more detail.
Product Specification
R

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