XC5VLX30T-1FF665I Xilinx Inc, XC5VLX30T-1FF665I Datasheet - Page 32

• Manufacturer Part Number: XC5VLX30T-1FF665I
• Description: FPGA Virtex®-5 Family 30720 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX30T-1FF665I

• Package: 665FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 30720
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 360
• Ram Bits: 1327104
• Number Of Logic Elements/cells: 30720
• Number Of Labs/clbs: 2400
• Total Ram Bits: 1327104
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IOB Pad Input/Output/3-State Switching Characteristics
Table 56
input delay adjustments, output delays terminating at pads
(based on standard) and 3-state delays.
T
input buffer to the I-pin of an IOB pad. The delay varies
depending on the capability of the SelectIO input buffer.
T
pad through the output buffer of an IOB pad. The delay
varies depending on the capability of the SelectIO output
buffer.
Table 56: IOB Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
LVDS_25
LVDSEXT_25
HT_25
BLVDS_25
RSDS_25 (point to point)
ULVDS_25
PCI33_3
PCI66_3
PCI-X
GTL
GTLP
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
HSTL_I _18
HSTL_II _18
HSTL_III _18
HSTL_IV_18
SSTL2_I
SSTL2_II
LVTTL, Slow, 2 mA
LVTTL, Slow, 4 mA
LVTTL, Slow, 6 mA
LVTTL, Slow, 8 mA
LVTTL, Slow, 12 mA
LVTTL, Slow, 16 mA
LVTTL, Slow, 24 mA
IOPI
IOOP
is described as the delay from IOB pad through the
is described as the delay from the O pin to the IOB
summarizes the values of standard-specific data
I/O Standard
0.80
1.01
0.80
0.80
0.80
0.80
0.62
0.62
0.62
0.76
0.76
0.76
0.76
0.76
0.76
0.76
0.76
0.76
0.76
0.76
0.76
0.62
0.62
0.62
0.62
0.62
0.62
0.62
-3
Speed Grade
T
0.90
1.16
0.90
0.90
0.90
0.90
0.70
0.70
0.70
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.70
0.70
0.70
0.70
0.70
0.70
0.70
IOPI
-2
www.xilinx.com
1.06
1.30
1.06
1.06
1.06
1.06
0.82
0.82
0.82
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
0.82
0.82
0.82
0.82
0.82
0.82
0.82
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
-1
T
pad through the output buffer of an IOB pad, when 3-state is
disabled. The delay varies depending on the SelectIO
capability of the output buffer.
Table 57
described as the delay from the T pin to the IOB pad
through the output buffer of an IOB pad, when 3-state is
enabled (i.e., a high impedance state).
IOTP
1.13
1.17
1.10
1.24
1.13
1.10
1.85
1.85
1.40
1.47
1.51
1.42
1.39
1.44
1.44
1.40
1.36
1.45
1.41
1.48
1.40
4.10
2.87
2.66
2.09
1.94
1.84
1.87
-3
Speed Grade
is described as the delay from the T pin to the IOB
summarizes the value of T
T
1.26
1.68
1.29
1.34
1.38
1.29
1.27
2.06
2.06
1.56
1.63
1.57
1.53
1.60
1.60
1.55
1.51
1.61
1.57
1.64
1.55
4.47
3.09
2.91
2.30
2.15
2.04
2.07
IOOP
-2
1.44
1.49
1.40
1.58
1.44
1.41
2.38
2.38
1.80
1.86
1.93
1.79
1.74
1.85
1.83
1.77
1.72
1.85
1.81
1.87
1.76
5.01
3.41
3.29
2.61
2.46
2.34
2.38
-1
1.13
1.17
1.10
1.24
1.13
1.10
1.85
1.85
1.40
1.47
1.51
1.42
1.39
1.44
1.44
1.40
1.36
1.45
1.41
1.48
1.40
4.10
2.87
2.66
2.09
1.94
1.84
1.87
-3
Speed Grade
IOTPHZ
T
1.29
1.34
1.26
1.38
1.29
1.27
2.06
2.06
1.56
1.63
1.68
1.57
1.53
1.60
1.60
1.55
1.51
1.61
1.57
1.64
1.55
4.47
3.09
2.91
2.30
2.15
2.04
2.07
IOTP
-2
. T
IOTPHZ
1.44
1.49
1.40
1.58
1.44
1.41
2.38
2.38
1.80
1.86
1.93
1.79
1.74
1.85
1.83
1.77
1.72
1.85
1.81
1.87
1.76
5.01
3.41
3.29
2.61
2.46
2.34
2.38
-1
is
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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