CY2309SC-1T Cypress Semiconductor Corp, CY2309SC-1T Datasheet

Phase Locked Loops (PLL) 3. 3V ZDB Internal Feedck

CY2309SC-1T

Manufacturer Part Number
CY2309SC-1T
Description
Phase Locked Loops (PLL) 3. 3V ZDB Internal Feedck
Manufacturer
Cypress Semiconductor Corp
Type
Zero Delay PLL Clock Bufferr
Datasheets

Specifications of CY2309SC-1T

Number Of Circuits
1
Output Frequency Range
10 MHz to 133.33 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Package / Case
SOIC-16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY2309SC-1T
Manufacturer:
CYPRESS
Quantity:
8 000
Part Number:
CY2309SC-1T
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Cypress Semiconductor Corporation
Document #: 38-07140 Rev. *G
Features
Functional Description
The CY2309 is a low-cost 3.3V zero delay buffer designed to
distribute high-speed clocks and is available in a 16-pin SOIC
or TSSOP package. The CY2305 is an 8-pin version of the
Block Diagram
• 10-MHz to 100-/133-MHz operating range, compatible
• Zero input-output propagation delay
• 60 ps typical cycle-to-cycle jitter (high drive)
• Multiple low-skew outputs
• Compatible with Pentium
• Test Mode to bypass phase-locked loop (PLL) (CY2309
• Available in space-saving 16-pin 150-mil SOIC or
• 3.3V operation
• Industrial temperature available
REF
with CPU and PCI bus frequencies
— 85 ps typical output-to-output skew
— One input drives five outputs (CY2305)
— One input drives nine outputs, grouped as 4 + 4 + 1
only [see “Select Input Decoding” on page 2])
4.4-mm TSSOP packages (CY2309), and 8-pin, 150-mil
SOIC package (CY2305)
S2
S1
(CY2309)
PLL
-based systems
Select Input
Decoding
MUX
3901 North First Street
Low-Cost 3.3V Zero Delay Buffer
CY2309. It accepts one reference input, and drives out five
low-skew clocks. The -1H versions of each device operate at
up to 100-/133-MHz frequencies, and have higher drive than
the -1 devices. All parts have on-chip PLLs which lock to an
input clock on the REF pin. The PLL feedback is on-chip and
is obtained from the CLKOUT pad.
The CY2309 has two banks of four outputs each, which can
be controlled by the Select inputs as shown in the “Select Input
Decoding” table on page 2. If all output clocks are not required,
BankB can be three-stated. The select inputs also allow the
input clock to be directly applied to the outputs for chip and
system testing purposes.
The CY2305 and CY2309 PLLs enter a power-down mode
when there are no rising edges on the REF input. In this state,
the outputs are three-stated and the PLL is turned off, resulting
in less than 12.0 µA of current draw for commercial temper-
ature devices and 25.0 µA for industrial temperature parts. The
CY2309 PLL shuts down in one additional case as shown in
the table below.
Multiple CY2305 and CY2309 devices can accept the same
input clock and distribute it. In this case, the skew between the
outputs of two devices is guaranteed to be less than 700 ps.
The CY2305/CY2309 is available in two/three different config-
urations, as shown in the ordering information (page 10). The
CY2305-1/CY2309-1 is the base part. The CY2305-1H/
CY2309-1H is the high-drive version of the -1, and its rise and
fall times are much faster than the -1s.
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
San Jose
CLKB1
CLKB2
CLKA1
CLKA2
GND
REF
Pin Configuration
V
S2
CLK2
CLK1
DD
GND
REF
,
SOIC/TSSOP
CA 95134
1
2
3
4
5
6
7
8
Top View
1
2
3
4
Top View
SOIC
Revised August 4, 2005
15
14
13
12
11
10
16
9
8
7
6
5
CLKOUT
CLK4
V
CLK3
CLKOUT
CLKA4
CLKA3
V
GND
CLKB4
CLKB3
S1
DD
DD
408-943-2600
CY2305
CY2309
[+] Feedback

Related parts for CY2309SC-1T

CY2309SC-1T Summary of contents

Page 1

... PLL REF S2 Select Input Decoding S1 Cypress Semiconductor Corporation Document #: 38-07140 Rev. *G Low-Cost 3.3V Zero Delay Buffer CY2309. It accepts one reference input, and drives out five low-skew clocks. The -1H versions of each device operate 100-/133-MHz frequencies, and have higher drive than the -1 devices. All parts have on-chip PLLs which lock to an input clock on the REF pin ...

Page 2

Pin Description for CY2309 Pin Signal [1] 1 REF [2] 2 CLKA1 [2] 3 CLKA2 GND [2] 6 CLKB1 [2] 7 CLKB2 [ [ [2] 10 CLKB3 [2] 11 CLKB4 12 GND ...

Page 3

REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB Pins Zero Delay and Skew Control All outputs should be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the internal ...

Page 4

... Absolute Maximum Conditions Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Input Voltage (Except REF) ............–0. Input Voltage REF......................................... –0. Operating Conditions for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices Parameter V Supply Voltage DD T Operating Temperature (Ambient Temperature Load Capacitance, below 100 MHz L C Load Capacitance, from 100 MHz to 133 MHz ...

Page 5

... Switching Characteristics for CY2305SC-1H and CY2309SC-1H Commercial Temperature Devices Parameter Name t1 Output Frequency [6] ÷ t Duty Cycle = [6] ÷ t Duty Cycle = [6] t3 Rise Time [6] t Fall Time 4 [6] t Output to Output Skew 5 t Delay, REF Rising Edge to 6A [6] CLKOUT Rising Edge t Delay, REF Rising Edge to ...

Page 6

Switching Characteristics for CY2305SI-1and CY2309SI-1 Industrial Temperature Devices Parameter Name t1 Output Frequency [6] ÷ t Duty Cycle = [6] t3 Rise Time [6] t Fall Time 4 [6] t Output to Output Skew 5 t Delay, ...

Page 7

Switching Waveforms Duty Cycle Timing 1.4V 1.4V All Outputs Rise/Fall Time 2.0V 2.0V OUTPUT 0. Output-Output Skew 1.4V OUTPUT 1.4V OUTPUT t 5 Input-Output Propagation Delay INPUT OUTPUT ...

Page 8

Typical Duty Cycle and I Trends DD Duty Cycle Vs VDD (for 30 pF Loads over Frequency - 3.3V, 25C 3.1 3.2 3.3 3.4 3.5 VDD (V) ...

Page 9

Typical Duty Cycle and IDD Trends Duty Cycle Vs VDD (for 30 pF Loads over Frequency - 3.3V, 25C 3.1 3.2 3.3 3.4 VDD (V) Duty Cycle ...

Page 10

... SOIC – (Lead-free) CY2305SXI-1HT 8-pin 150-mil SOIC – Tape and Reel – (Lead-free) CY2309SC-1 16-pin 150-mil SOIC CY2309SC-1T 16-pin 150-mil SOIC – Tape and Reel CY2309SZC-1 16-pin 150-mil SOIC – (Lead-free) CY2309SZC-1T 16-pin 150-mil SOIC – Tape and Reel – (Lead-free) CY2309SXC-1 16-pin 150-mil SOIC – ...

Page 11

... SOIC – (Lead-free) CY2309SXI-1T 16-pin 150-mil SOIC – Tape and Reel – (Lead-free) CY2309SC-1H 16-pin 150-mil SOIC CY2309SC-1HT 16-pin 150-mil SOIC – Tape and Reel CY2309SZC-1H 16-pin 150-mil SOIC – (Lead-free) CY2309SZC-1HT 16-pin 150-mil SOIC – Tape and Reel – (Lead-free) CY2309SXC-1H 16-pin 150-mil SOIC – ...

Page 12

Package Drawing and Dimensions 8 Lead (150 Mil) SOIC - S08 0.189[4.800] 0.196[4.978] 0.050[1.270] BSC 0.0138[0.350] 0.0192[0.487] 16 Lead (150 Mil) SOIC 8 9 0.386[9.804] 0.393[9.982] 0.050[1.270] BSC 0.0138[0.350] 0.0192[0.487] Document #: 38-07140 Rev. *G 8-lead ...

Page 13

... Document #: 38-07140 Rev. *G © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

Page 14

... HWT Added eight-pin TSSOP packages (CY2305ZC-1 and CY2305ZC-1T) to the ordering information table. Added the Tape and Reel option to all the existing packages: CY2305SC-1T, CY2305SI-1T, CY2305SC-1HT, CY2305SI-1HT, CY2305ZC-1T, CY2309SC-1T, CY2309SI-1T, CY2309SC-1HT, CY2309SI-1HT, CY2309ZC-1HT, CY2309ZI-1HT RBI Power-up requirements added to Operating Conditions information RGL ...

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