Si4330-V2-FM Silicon Laboratories Inc, Si4330-V2-FM Datasheet - Page 29

• Manufacturer Part Number: Si4330-V2-FM
• Description: RF Receiver RECEIVER EZRadioPRO UNIVERSAL ISM BAND
• Manufacturer: Silicon Laboratories Inc
• Type: ISM Receiverr

Specifications of Si4330-V2-FM

• Package / Case: QFN-20
• Operating Frequency: 240 MHz to 960 MHz
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 100 nA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5. Internal Functional Blocks
This section provides an overview some of the key blocks of the internal radio architecture.
5.1. RX LNA
The input frequency range for the LNA is between 240–960 MHz. The LNA provides gain with a noise figure low
enough to suppress the noise of the following stages. The LNA has one step of gain control which is controlled by
the analog gain control (AGC) algorithm. The AGC algorithm adjusts the gain of the LNA and PGA so the receiver
can handle signal levels from sensitivity to +5 dBm with optimal performance.
5.2. RX I-Q Mixer
The output of the LNA is fed internally to the input of the receive mixer. The receive mixer is implemented as an I-Q
mixer that provides both I and Q channel outputs to the programmable gain amplifier. The mixer consists of two
double-balanced mixers whose RF inputs are driven in parallel, local oscillator (LO) inputs are driven in quadrature,
and separate I and Q Intermediate Frequency (IF) outputs drive the programmable gain amplifier. The receive LO
signal is supplied by an integrated VCO and PLL synthesizer operating between 240–960 MHz. The necessary
quadrature LO signals are derived from the divider at the VCO output.
5.3. Programmable Gain Amplifier
The programmable gain amplifier (PGA) provides the necessary gain to boost the signal level into the dynamic
range of the ADC. The PGA must also have enough gain switching to allow for large input signals to ensure a
linear RSSI range up to –20 dBm. The PGA has steps of 3 dB which are controlled by the AGC algorithm in the
digital modem.
5.4. ADC
The amplified IQ IF signals are digitized using an Analog-to-Digital Converter (ADC), which allows for low current
consumption and high dynamic range. The bandpass response of the ADC provides exceptional rejection of out of
band blockers.
5.5. Digital Modem
Using high-performance ADCs allows channel filtering, image rejection, and demodulation to be performed in the
digital domain, resulting in reduced area while increasing flexibility. The digital modem performs the following
functions:
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The digital channel filter and demodulator are optimized for ultra low power consumption and are highly
configurable. Supported modulation types are GFSK, FSK, and OOK. The channel filter can be configured to
support bandwidths ranging from 620 kHz down to 2.6 kHz. A large variety of data rates are supported ranging
from 0.123 up to 256 kbps. The AGC algorithm is implemented digitally using an advanced control loop optimized
for fast response time.
The configurable preamble detector is used to improve the reliability of the sync-word detection. The sync-word
detector is only enabled when a valid preamble is detected, significantly reducing the probability of false detection.
The received signal strength indicator (RSSI) provides a measure of the signal strength received on the tuned
channel. The resolution of the RSSI is 0.5 dB. This high resolution RSSI enables accurate channel power
Channel selection filter
RX demodulation
AGC
Preamble detector
Invalid preamble detector
Radio signal strength indicator (RSSI)
Automatic frequency compensation (AFC)
Packet handling including EZMac
Cyclic redundancy check (CRC)
TM
features
Rev 1.0
Si4330-B1
29