CY2DP818ZC-2 Cypress Semiconductor Corp, CY2DP818ZC-2 Datasheet

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CY2DP818ZC-2

Manufacturer Part Number
CY2DP818ZC-2
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY2DP818ZC-2

Number Of Outputs
16
Operating Supply Voltage (max)
3.465V
Operating Temp Range
0C to 70C
Propagation Delay Time
6ns
Operating Supply Voltage (min)
3.135V
Mounting
Surface Mount
Pin Count
38
Operating Supply Voltage (typ)
3.3V
Package Type
TSSOP
Input Frequency
350MHz
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Not Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
CY2DP818ZC-2
Manufacturer:
CY
Quantity:
813
Cypress Semiconductor Corporation
Document #: 38-07588 Rev. *A
Features
Logic Block Diagram
Low voltage operation V
1:8 fanout
Single-input configurable for LVDS, LVPECL, or LVTTL
8 pairs of LVPECL outputs with enable and disable
Drives a 50 ohm load
Low input capacitance
Low output skew
Low propagation delay typical (tpd < 4 ns)
Industrial versions available
Package available include: TSSOP
Does not exceed Bellcore 802.3 standards
Operation up to 350 MHz and 700 Mbps
DD
= 3.3V
INPUT A
INPUT B
InConfig
(LVPECL / LVDS / LVTTL)
PRELIMINARY
198 Champion Court
INPUT
EN7
EN4
EN5
EN6
EN1
EN2
EN3
Description
This Cypress series of network circuits is produced using
advanced 0.35 micron CMOS technology, achieving the
industry’s fastest logic.
The Cypress CY2DP818-2 fanout buffer features a single
LVDS or a single-ended LVTTL compatible input and eight
LVPECL output pairs.
Designed for data communications clock management appli-
cations, the large fanout from a single input reduces loading
on the input clock.
The CY2DP818-2 is ideal for both level translations from
single-ended to LVPECL and for the distribution of LVPECL
based clock signals.
The Cypress CY2DP818-2 has configurable input functions.
The input is user configurable through the Inconfig pin for
single ended or differential input.
OUTPUT
San Jose
(LVPECL)
1:8 Clock Fanout Buffer
Q5A
Q3A
Q3B
Q4A
Q4B
Q5B
Q6A
Q6B
Q7A
Q7B
Q8A
Q8B
Q1A
Q1B
Q2A
Q2B
,
CA 95134-1709
Revised October 22, 2008
CY2DP818-2
408-943-2600
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CY2DP818ZC-2 Summary of contents

Page 1

... Does not exceed Bellcore 802.3 standards ■ Operation up to 350 MHz and 700 Mbps ■ Logic Block Diagram Cypress Semiconductor Corporation Document #: 38-07588 Rev. *A PRELIMINARY Description This Cypress series of network circuits is produced using advanced 0.35 micron CMOS technology, achieving the industry’ ...

Page 2

Pin Configuration Pin Description Pin Number Pin Name 1, 9,12,18,19,20,38 GND 2,8,13,29,17 VDD 3,4,5,6,14,15,16 EN(1:7) 10,11 Input A, Input B 37, 36,35,34, Q1(A,B), Q2(A,B) 33,32,31, 30, Q3(A,B), Q4(A,B) 28,27,26,25, Q5(A,B), Q6(A,B) 24,23,22,21 Q7(A,B), Q8(A,B) 7 InConfig Document #: 38-07588 Rev. ...

Page 3

Power Supply Characteristics Parameter Description ICCD Dynamic Power Supply Current IC Total Power Supply Current IC Core Core Current when Output Loads are Disabled Input Receiver Configuration for Differential or LVTTL/LVCMOS INCONFIG Pin 7 Input Receiver Family Binary Value 1 ...

Page 4

Absolute Maximum Conditions Parameter Description V DC Supply Voltage Operating Voltage Input Voltage Output Voltage OUT V Output Termination Voltage TT T Temperature, Storage S T Temperature, Operating A Ambient Multiple ...

Page 5

LVPECL Output 3.3V ± 5 Parameter Description V Driver Differential Output Voltage p-p OD ΔV Driver common-Mode Variation p-p OC Rise Time Differential 20% to 80% Fall Time V Output High Voltage OH ...

Page 6

Figure 3. Differential Receiver to Driver Propagation Delay and Driver Transition Time A Pulse Generator B INA 1 INB QXA 1 QXB Figure 4. Test Circuit and Voltage Definitions for the Driver Common-Mode Output Voltage Pulse ...

Page 7

... I(B) [6] Figure 6. LVTTL/LVCMOS INPUT A LVCM OS / LVTTL INPUT B GND InConfig LVTTL/LVCMOS 1 Ordering Information Part Number CY2DP818ZI-2 CY2DP818ZI-2T CY2DP818ZC-2 CY2DP818ZC-2T Pb Free Devices CY2DP818ZXI-2 CY2DP818ZXI-2T CY2DP818ZXC-2 CY2DP818ZXC-2T Note 6. LVPECL or LVDS differential input value. Document #: 38-07588 Rev. *A PRELIMINARY 150 10pF GND 150 Standard Termination 1.4V 1 ...

Page 8

Package Drawing and Dimensions Document #: 38-07588 Rev. *A PRELIMINARY Figure 8. 38-Pin TSSOP (4.40 mm Body) Z38 CY2DP818-2 51-85151-*A Page [+] Feedback [+] Feedback [+] Feedback ...

Page 9

... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...

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