CY2DP3110AI Cypress Semiconductor Corp, CY2DP3110AI Datasheet - Page 4

• Manufacturer Part Number: CY2DP3110AI
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Driverr

Specifications of CY2DP3110AI

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 1500MHz
• Output Logic Level: ECL/PECL
• Operating Supply Voltage (min): -2.375/2.375V
• Operating Supply Voltage (typ): -2.5/-3.3/2.5/3.3V
• Operating Supply Voltage (max): -3.465/3.465V
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: ECL/HSTL/PECL
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-07469 Rev. *I
ECL DC Electrical Specifications
AC Electrical Specifications
V
V
V
V
V
V
V
V
V
F
T
V
V
tsk
tsk
t
t
tsk
T
Notes:
12. V
13. 50% duty cycle; standard load; differential operation.
14. Typical jitter measurements are taken at room temperature and nominal voltage. For further information regarding jitter, please refer to the Application note
15. Output pulse skew is the absolute difference of the propagation delay times: | t
jit(per)
jit(pn)
Parameter
Parameter
CLK
PD
R
EE
CMR
OH
OL
IH
IL
BB
PP
CMRO
DIF
O
,T
(O)
(PP)
(P)
“Understanding Data sheet Jitter Specifications for Cypress Timing Products.”
[3]
DIF
F
(AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tkpd and device-to-device skew.
Negative Power Supply
ECL Input Differential Cross Point
Voltage
Output High Voltage
Output Low Voltage
V
V
Input Voltage, High
Input Voltage, Low
Output Reference Voltage
PECL/ECL Differential Input Voltage
Output Common Voltage Range (typ.)
Input Frequency
Propagation Delay CLKA or CLKB to
Output pair
HSTL Differential Input Voltage
Output Voltage
(peak-to-peak; see Figure 2)
Output-to-output Skew
Part-to-Part Output Skew
Output Period Jitter (peak)
Output RMS Phase Jitter
(See Figure 6)
Output Pulse Skew
Output Rise/Fall Time (see Figure 2)
EE
EE
= –3.3V ± 5%
= –2.5V ± 5%
[8]
[13]
Description
Description
[15]
[13, 14]
[13]
[14]
[12]
[8]
–2.5V ± 5%, V
–3.3V ± 5%, V
Differential operation
I
I
Single-ended operation
Single-ended operation
Differential operation
50% duty cycle Standard load
PECL, ECL < 660 MHz
HSTL < 1 GHz
Duty Cycle Standard Load
Differential Operation
< 1 GHz
<660 MHz
156.25 MHz
156.25 MHz, 3.3V, broadband
156.25 MHz, 3.3V, filtered
312.5 MHz, 3.3V, broadband
312.5 MHz, 3.3V, filtered
660 MHz
Differential 20% to 80%
OH
OL
50% duty cycle
= –5 mA
= –30 mA
[13]
Condition
PLH
Condition
[13]
[10]
, See Figure 3
[13]
– t
, See Figure 3
[10]
CC
CC
PHL
= 0.0V
= 0.0V
|.
0.375
–1.945
V
Min.
0.08
280
280
0.1
0.4
–2.625
–3.465
–1.995
–1.995
–1.165
EE
–1.620
–
–
–
–
–
–
–
–
–
–1.25
Min.
+ 1.2
FastEdge™ Series
[11]
V
CC
0.165
0.151
0.141
0.107
Typ.
400
400
7.2
– 1.425
29
95
–
–
–
–
–0.880
CY2DP3110
–2.375
–3.135
–1.625
–1.220
Max.
–0.7
–1.5
–1.3
0V
Max.
650
750
150
1.3
1.5
1.9
0.3
50
15
50
–
–
–
[11]
–
–
Page 4 of 10
Unit
GHz
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
V
V
V
V
V
V
V
V
V
V
V