ICS87008AGIT IDT, Integrated Device Technology Inc, ICS87008AGIT Datasheet

ICS87008AGIT

Manufacturer Part Number

ICS87008AGIT

Description

Manufacturer

IDT, Integrated Device Technology Inc

Type

Clock Dividerr

Datasheet

1.ICS87008AGIT.pdf (16 pages)

Specifications of ICS87008AGIT

Number Of Clock Inputs

Output Frequency

250MHz

Output Logic Level

LVCMOS/LVTTL

Operating Supply Voltage (min)

2.375V

Operating Supply Voltage (typ)

2.5/3.3V

Operating Supply Voltage (max)

3.465V

Package Type

TSSOP

Operating Temp Range

-40C to 85C

Operating Temperature Classification

Industrial

Mounting

Surface Mount

Pin Count

Lead Free Status / RoHS Status

Not Compliant

Current page: 1 of 16
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The ICS87008I is a low skew, 1:8 LVCMOS/LVTTL Clock

Generator. The device has 2 banks of 4 outputs and each

bank can be independently selected for 1 or 2 frequency

operation. Each bank also has its own power supply pins so

that the banks can operate at the following different voltage

levels: 3.3V, 2.5V, and 1.8V. The low impedance LVCMOS/

LVTTL outputs are designed to drive 50

terminated transmission lines.

The divide select inputs, DIV_SELA and DIV_SELB, control the

output frequency of each bank. The output banks can be

independently selected for 1 or 2 operation. The bank enable

inputs, CLK_ENA and CLK_ENB, support enabling and disabling

each bank of outputs individually. The CLK_ENA and CLK_ENB

circuitry has a synchronizer to prevent runt pulses when

enabling or disabling the clock outputs. The master reset

input, nMR/OE, resets the 1/ 2 flip flops and also controls the

active and high impedance states of all outputs. This pin has

an internal pull-up resistor and is normally used only for test

purposes or in systems which use low power modes.

The ICS87008I is characterized to operate with the core at 3.3V

or 2.5V and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed bank,

output, and part-to-part skew characteristics make the 87008I

ideal for those clock applications demanding well-defined

performance and repeatability.

DIV_SELA

87008AGI

CLK_ENA

CLK_ENB

DIV_SELB

CLK_SEL

nMR/OE

LOCK

ENERAL

nCLK1

CLK1

CLK0

IAGRAM

ESCRIPTION

series or parallel

IFFERENTIAL

www.idt.com

• Eight LVCMOS/LVTTL outputs (2 banks of 4 outputs)

• Selectable differential CLK1, nCLK1 or

• CLK1, nCLK1 pair can accept the following differential

• CLK0 supports the following input types:

• Maximum output frequency: 250MHz

• Independent bank control for 1 or 2 operation

• Glitchless, asynchronous clock enable/disable

• Output skew: 105ps (maximum) @ 3.3V core/3.3V output

• Bank skew: 70ps (maximum) @ 3.3V core/3.3V output

• 3.3V or 2.5V core/3.3V, 2.5V, or 1.8V output operating

• -40°C to 85°C ambient operating temperature

• Available in both standard and lead-free RoHS compliant

QA0:QA3

QB0:QB3

LVCMOS clock input

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

LVCMOS, LVTTL

supply

packages

EATURES

-LVCMOS/LVTTL C

SSIGNMENT

4.4mm x 7.8mm x 0.92mm body package

DIV_SELA

CLK_ENA

nCLK1

CLK1

GND

QA0

QA1

QA2

QA3

DDOA

24-Lead TSSOP

ICS87008I

G Package

Top View

LOCK

ICS87008I

CLK0

CLK_SEL

QB0

QB1

GND

QB2

QB3

DIV_SELB

CLK_ENB

nMR/OE

DDOB

KEW

REV. B JULY 31, 2010

ENERATOR

, 1-

-8

Related parts for ICS87008AGIT

ICS87008AGIT Summary of contents

Page 1

G D ENERAL ESCRIPTION The ICS87008I is a low skew, 1:8 LVCMOS/LVTTL Clock Generator. The device has 2 banks of 4 outputs and each bank can be independently selected for frequency operation. Each bank also has its ...

Page 2

ABLE IN ESCRIPTIONS ...

Page 3

BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs, V -0. Package Thermal Impedance, JA Storage Temperature, T -65°C to 150°C STG T 4A ABLE ...

Page 4

T 4B. LVCMOS/LVTTL DC C ABLE HARACTERISTICS ...

Page 5

T 5A ABLE HARACTERISTICS ...

Page 6

T 5C 3.3V±5%, V ABLE HARACTERISTICS ...

Page 7

T 5E ABLE HARACTERISTICS ...

Page 8

P ARAMETER 1.65V± DDOA, DDOB LVCMOS GND -1.65V±5% 3.3V C /3. ORE UTPUT OAD 2.05V±5% 1.25V± DDOA, DDOB LVCMOS GND -1.25V±5% 3.3V C /2. ...

Page 9

PART 1 V DDOX Qx 2 PART 2 V DDOX sk(pp ART TO ART KEW V DDOX 2 QX0:QX0 V DDOX 2 QX0:QX0 t sk( where X denotes outputs in ...

Page 10

IRING THE IFFERENTIAL NPUT TO Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 and C1. This bias ...

Page 11

IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING the V and V input requirements. Figures show PP CMR interface examples for ...

Page 12

ABLE VS IR LOW ABLE FOR JA Multi-Layer PCB, JEDEC Standard Test Boards T C RANSISTOR OUNT The transistor count for ICS87008I is: 1262 87008AGI D - -LVCMOS/LVTTL C IFFERENTIAL ELIABILITY ...

Page 13

ACKAGE UTLINE UFFIX FOR T ABLE S Reference Document: JEDEC Publication 95, MS-153 87008AGI D - -LVCMOS/LVTTL C IFFERENTIAL TO TSSOP EAD ACKAGE IMENSIONS ...

Page 14

ABLE RDERING NFORMATION ...

Page 15

...

Page 16

We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of ...

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