ICS85104AGI IDT, Integrated Device Technology Inc, ICS85104AGI Datasheet

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ICS85104AGI

Manufacturer Part Number
ICS85104AGI
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Datasheet

Specifications of ICS85104AGI

Number Of Clock Inputs
2
Output Frequency
500MHz
Output Logic Level
HCSL
Operating Supply Voltage (min)
2.97V
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.63V
Package Type
TSSOP
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
20
Lead Free Status / RoHS Status
Not Compliant

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Part Number
Manufacturer
Quantity
Price
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Manufacturer:
IDT
Quantity:
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IDT
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8 000
Part Number:
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IDT
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LOW SKEW, 1-TO-4, DIFFERENTIAL/
LVCMOS-TO-0.7V HCSL FANOUT BUFFER
B
IDT
G
The CLK0, nCLK0 pair can accept most standard differential
input levels. The single-ended CLK1 can accept LVCMOS or
LVTTL input levels. The clock enable is internally synchronized
to eliminate runt clock pulses on the outputs during asynchro-
nous assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make
the ICS85104I ideal for those applications demanding well
defined performance and repeatability.
HiPerClockS™
CLK_SEL
IC S
CLK_EN
LOCK
ENERAL
nCLK0
CLK0
CLK1
IREF
/ ICS
Pullup
Pulldown
Pullup/Pulldown
Pulldown
Pulldown
0.7V HCSL FANOUT BUFFER
D
The ICS85104I is a low skew, high performance 1-
to-4 Differential/LVCMOS-to-0.7V HCSL Fanout
Buffer and a member of the HiPerClockS™ family
of High Performance Clock Solutions from IDT.
The ICS85104I has two selectable clock inputs.
IAGRAM
D
ESCRIPTION
0
1
D
LE
Q
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
1
F
Four 0.7V differential HCSL outputs
Selectable differential CLK0, nCLK0 or LVCMOS inputs
CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 500MHz
Translates any single-ended input signal to 3.3V
HCSL levels with resistor bias on nCLK input
Output skew: 100ps (maximum)
Part-to-part skew: 600ps (maximum)
Propagation delay: 3.2ns (maximum)
Additive phase jitter, RMS: 0.22ps (typical)
3.3V operating supply
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
EATURES
P
6.5mm x 4.4mm x 0.925mm Package Body
IN
A
CLK_SEL
SSIGNMENT
CLK_EN
nCLK0
CLK0
CLK1
IREF
GND
V
20-Lead TSSOP
nc
nc
DD
ICS85104I
ICS85104AGI REV. A FEBRUARY 25, 2009
G Package
Top View
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
Q1
nQ1
Q2
nQ2
V
Q3
nQ3
DD
DD
ICS85104I

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ICS85104AGI Summary of contents

Page 1

... Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Q Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 1 ICS85104I SSIGNMENT GND CLK_EN 2 19 nQ0 CLK_SEL CLK0 nCLK0 5 16 nQ1 CLK1 nQ2 IREF nQ3 ICS85104I 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm Package Body G Package Top View ICS85104AGI REV. A FEBRUARY 25, 2009 ...

Page 2

... ICS85104I LOW SKEW, 1-TO-4, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER ABLE IN ESCRIPTIONS ABLE IN HARACTERISTICS IDT ™ / ICS ™ 0.7V HCSL FANOUT BUFFER ICS85104AGI REV. A FEBRUARY 25, 2009 ...

Page 3

... ICS85104I LOW SKEW, 1-TO-4, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER ABLE ONTROL NPUT UNCTION ABLE Disabled nCLK0 CLK0, CLK1 CLK_EN nQ0:nQ3 Q0:Q3 IDT ™ / ICS ™ 0.7V HCSL FANOUT BUFFER CLK_EN T D IGURE IMING IAGRAM Enabled ICS85104AGI REV. A FEBRUARY 25, 2009 ...

Page 4

... DC Characteristics or AC Characteristics is not 91.1°C/W (0 mps) implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability 3.3V±10 -40° 3.3V±10 -40°C HARACTERISTICS 3.3V±10 -40° 85° 85° 85° ICS85104AGI REV. A FEBRUARY 25, 2009 µ A µ A µ A µ µ A µ A µ ...

Page 5

... ICS85104I LOW SKEW, 1-TO-4, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER 3.3V±10%, T ABLE HARACTERISTICS ƒ IDT ™ / ICS ™ 0.7V HCSL FANOUT BUFFER = -40°C 85° ± ± ICS85104AGI REV. A FEBRUARY 25, 2009 ...

Page 6

... F (H FFSET ROM ARRIER REQUENCY device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. 6 Additive Phase Jitter, 100MHz = 0.22ps (typical ICS85104AGI REV. A FEBRUARY 25, 2009 ...

Page 7

... V CMR ART TO ART KEW nCLK0 CLK0 nQ0:nQ3 Q0: ROPAGATION ELAY Rise Edge Rate +150mV 0.0V -150mV IFFERENTIAL EASUREMENT 49.9 2pF 50 33 nQx 49.9 2pF EST IRCUIT tsk(pp IFFERENTIAL NPUTS Fall Edge Rate OINTS FOR ISE ALL IME ICS85104AGI REV. A FEBRUARY 25, 2009 ...

Page 8

... P A EASUREMENT OINTS FOR BSOLUTE IDT ™ / ICS ™ 0.7V HCSL FANOUT BUFFER M I EASUREMENT NFORMATION nQ Negative Duty Cycle (Differential) V CROSS_DELTA UTY YCLE ERIOD EASUREMENT STABLE R INGBACK ROSS OINT WING 8 , CONTINUED = 140mV OINTS FOR ELTA ROSS OINT ICS85104AGI REV. A FEBRUARY 25, 2009 ...

Page 9

... For example, if the input DD clock swing is only 2.5V and V and R2/R1 = 0.609 Single Ended Clock Input V_Bias C1 0. INGLE NDED IGNAL RIVING UTPUT = 3.3V, V_BIAS should be 1.25V DD CLK nCLK D I IFFERENTIAL NPUT ICS85104AGI REV. A FEBRUARY 25, 2009 ...

Page 10

... NPUT RIVEN OUPLE 10 3. Ohm CLK Ohm nCLK HiPerClockS LVPECL Input 3B CLK/ CLK LOCK N NPUT 3.3V LVPECL D RIVER Ohm LVDS_Driv er R1 100 Ohm 3D CLK/ CLK LOCK N NPUT 3.3V LVDS D RIVER ICS85104AGI REV. A FEBRUARY 25, 2009 D RIVEN BY 3.3V CLK nCLK Receiv er D RIVEN BY ...

Page 11

... Figure 4B is the recommended termination for applications which require a point to point connection and contain the driver IDT ™ / ICS ™ 0.7V HCSL FANOUT BUFFER F 4A IGURE ECOMMENDED ERMINATION and receiver on the same PCB. All traces should all be 50 impedance IGURE ECOMMENDED ERMINATION 11 ICS85104AGI REV. A FEBRUARY 25, 2009 ...

Page 12

... OWER ONSIDERATIONS = 3.3V + 10% = 3.63V, which gives worst case results 3.63V * 27mA = 98.01mW TM * Pd_total + 20-L TSSOP EADN ORCED ONVECTION by Velocity (Meters per Second 91.1°C/W 12 devices is 125°C. must be used. Assuming no air JA 1 2.5 86.7°C/W 84.6°C/W ICS85104AGI REV. A FEBRUARY 25, 2009 ...

Page 13

... DD_HIGH L OUT OUT = (3.63V – 17mA * 17mA Total Power Dissipation per output pair = 47.3mW IDT ™ / ICS ™ 0.7V HCSL FANOUT BUFFER OUT = 17mA HCSL D C IGURE RIVER IRCUIT AND load to ground. is HIGH OUT 13 V OUT ERMINATION ICS85104AGI REV. A FEBRUARY 25, 2009 ...

Page 14

... HCSL FANOUT BUFFER R I ELIABILITY NFORMATION 20 L TSSOP EAD by Velocity (Meters per Second 91.1°C/W O ACKAGE UTLINE AND T TSSOP ABLE EAD Reference Document: JEDEC Publication 95, MO-153 14 1 2.5 86.7°C/W 84.6°C/W D IMENSIONS ACKAGE IMENSIONS ° ICS85104AGI REV. A FEBRUARY 25, 2009 ° ...

Page 15

... IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS ™ 0.7V HCSL FANOUT BUFFER " " " " " " ° & ° ° & ° ICS85104AGI REV. A FEBRUARY 25, 2009 ° ° ° ° ...

Page 16

ICS85104I LOW SKEW, 1-TO-4, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United ...

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