8535BG-01T IDT, Integrated Device Technology Inc, 8535BG-01T Datasheet - Page 10

• Manufacturer Part Number: 8535BG-01T
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of 8535BG-01T

• Number Of Clock Inputs: 2
• Mode Of Operation: Single-Ended
• Output Frequency: 266MHz
• Output Logic Level: LVPECL
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Signal Type: LVCMOS/LVTTL
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Not Compliant

This section provides information on power dissipation and junction temperature for the ICS8535-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8535-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
moderate air low of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6A below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
This calculation is only an example, and the Tj will obviously vary depending on the number of outputs that are loaded, supply
voltage, air flow, and the type of board (single layer or multi-layer).
T
IDT
T
ABLE
ABLE
ICS8535-01
LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
™
/ ICS
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
6A. T
6B.
Power (core)
Power (outputs)
If all outputs are loaded, the total power is 4 x 30mW = 120mW
Total Power
The equation for Tj is as follows: Tj =
Tj = Junction Temperature
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
70°C + 0.293W * 66.6°C/W = 89.5°C. This is well below the limit of 125°C.
™
Multi-Layer PCB, JEDEC Standard Test Boards
JA
A
3.3V LVPECL FANOUT BUFFER
= Ambient Temperature
= Junction-to-Ambient Thermal Resistance
JA
HERMAL
VS
. A
IR
MAX
R
_MAX
F
ESISTANCE
LOW
= V
MAX
(3.465V, with all outputs switching) = 173.25mW + 120mW = 293.25mW
= 30mW/Loaded Output pair
CC_MAX
T
ABLE FOR
* I
EE_MAX
JA
FOR
= 3.465V * 50mA = 173.25mW
20 L
20-L
CC
JA
= 3.3V + 5% = 3.465V, which gives worst case results.
EAD
P
by Velocity (Linear Feet per Minute)
JA
EAD
by Velocity (Meters per Second)
OWER
JA
VFQFN
* Pd_total + T
TSSOP, F
C
ORCED
ONSIDERATIONS
114.5°C/W
A
73.2°C/W
10
0
60.4°C/W
C
ONVECTION
0
TM
devices is 125°C.
98.0°C/W
66.6°C/W
200
52.8°C/W
1
ICS8535AG-01 REV. F OCTOBER 27, 2008
JA
88.0°C/W
63.5°C/W
must be used. Assuming a
500
46.0°C/W
3