5T93GL10NLI IDT, Integrated Device Technology Inc, 5T93GL10NLI Datasheet

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5T93GL10NLI

Manufacturer Part Number
5T93GL10NLI
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Datasheet

Specifications of 5T93GL10NLI

Number Of Clock Inputs
2
Mode Of Operation
Differential
Output Frequency
650MHz
Output Logic Level
LVDS
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (typ)
2.5V
Operating Supply Voltage (max)
2.7V
Package Type
VFQFPN
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
40
Quiescent Current
295mA
Lead Free Status / RoHS Status
Not Compliant
Pin Assignment
2.5V LVDS, 1:10 GLITCHLESS CLOCK BUFFER
TERABUFFER™ II
General Description
network. The IDT5T93GL10 can act as a translator from a
differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),
CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V
LVTTL input can also be used to translate to LVDS outputs. The
redundant input capability allows for a glitchless change-over
from a primary clock source to a secondary clock source.
Selectable inputs are controlled by SEL. During the switchover,
the output will disable low for up to three clock cycles of the
previously-selected input clock. The outputs will remain low for up
to three clock cycles of the newly-selected clock, after which the
outputs will start from the newly-selected input. A FSEL pin has
been implemented to control the switchover in cases where a
clock source is absent or is driven to DC levels below the minimum
specifications.
The IDT5T93GL10 outputs can be asynchronously
enabled/disabled. When disabled, the outputs will drive to the
value selected by the GL pin. Multiple power and grounds reduce
noise.
Applications
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II
HiPerClockS™
ICS
Clock distribution
GND
V
V
6mm x 6mm x 0.925mm package body
G1
Q1
Q2
Q1
Q2
A1
DD
DD
A1
1
2
3
4
5
6
7
8
9
10
The IDT5T93GL10 2.5V differential clock buffer is a
user-selectable differential input to ten LVDS
outputs . The fanout from a differential input to ten
LVDS outputs reduces loading on the preceding
driver and provides an efficient clock distribution
40 39 38 37 36 35 34 33 32 31
11 12 13 14 15 16 17 18 19 20
IDT5T93GL10
40-Lead VFQFPN
K package
Top View
30
29
28
27
26
25
24
23
22
21
G2
PD
V
Q7
Q7
Q6
Q6
V
A2
A2
DD
DD
FSEL
SEL
PD
GL
G1
G2
A1
A1
A2
A2
1
Block Diagram
Features
Guaranteed low skew: <25ps (maximum)
Very low duty cycle distortion: <100ps (maximum)
High speed propagation delay: <2ns (maximum)
Up to 650MHz operation
Glitchless input clock switching
Selectable inputs
Hot insertable and over-voltage tolerant inputs
3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL
(3.3V), CML or LVDS input interfaces
Selectable differential inputs to ten LVDS outputs
Power-down mode
At power-up, FSEL should be LOW
2.5V V
-40°C to 85°C ambient operating temperature
Available in VFQFPN package
Recommends IDT5T9310 if glitchless input selection is not
required
DD
0
1
IDT5T93GL10 REV. A MARCH 18, 2009
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
IDT5T93GL10
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
Q8
Q8
Q9
Q9
Q10
Q10

Related parts for 5T93GL10NLI

5T93GL10NLI Summary of contents

Page 1

LVDS, 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER™ II General Description The IDT5T93GL10 2.5V differential clock buffer is a ICS user-selectable differential input to ten LVDS outputs . The fanout from a differential input to ten HiPerClockS™ LVDS outputs reduces loading ...

Page 2

IDT5T93GL10 06 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Table 1. Pin Descriptions Name Type A[1:2] Input Adjustable A[1:2] Input Adjustable G1 Input LVTTL G2 Input LVTTL GL Input LVTTL Q[1:10] Output LVDS Q{1:10} Output LVDS SEL Input LVTTL PD Input LVTTL ...

Page 3

IDT5T93GL10 2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Function Tables Table 3A. Gate Control Output Table Control Outputs GL G Q[1:16 Toggling 0 1 LOW 1 0 Toggling 1 1 HIGH Table 3B. Input Selection Table Selection ...

Page 4

IDT5T93GL10 06 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or ...

Page 5

IDT5T93GL10 2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Table 4B. LVTTL DC Characteristics Symbol Parameter I Input High Current IH I Input Low Current IL V Clamp Diode Voltage Input Voltage Input High ...

Page 6

IDT5T93GL10 06 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Table 4D. LVDS DC Characteristics Symbol Parameter Differential Output Voltage for the V OT(+) True Binary State Differential Output Voltage for the V OT(–) False Binary State Change in V Between Complementary ∆V ...

Page 7

IDT5T93GL10 2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Table 5B. eHSTL AC Differential Input Characteristics, T Symbol Parameter (1) V Input Signal Swing DIF V Differential Input Signal Crossing Point X D Duty Cycle H V Input Timing Measurement ...

Page 8

IDT5T93GL10 06 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Table 5E. AC Differential Input Characteristics Symbol Parameter ( Differential Voltage DIF V Differential Input Crosspoint Voltage IX V Common Mode Input Voltage Range CM V Input Voltage IN NOTE 1.The ...

Page 9

IDT5T93GL10 2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Differential AC Timing Waveforms Output Propagation and Skew Waveforms 1/ [1:2] [1:2] t PLH SK( NOTE 1: Pulse skew is calculated ...

Page 10

IDT5T93GL10 06 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Glitchless Output Operation with Switching Input Clock Selection SEL When SEL changes, the output clock goes LOW on the ...

Page 11

IDT5T93GL10 2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER™ II FSEL Operation for When Opposite Clock Dies 1. When the differential on the non-selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state. When this ...

Page 12

IDT5T93GL10 06 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Power Down Timing NOTE recommended that outputs be disabled before entering power-down mode ...

Page 13

IDT5T93GL10 2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Test Circuits and Conditions Test Circuit for Differential Input Pulse Generator Table 6A. Differential Input Test Conditions Symbol V = 2.5V ± 0. Crossing of A and A THI ...

Page 14

IDT5T93GL10 06 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Test Circuit for DC Outputs and Power Down Tests A Pulse Generator D.U.T. A Test Circuit for Propagation, Skew, and Gate Enable/Disable Timing A Pulse Generator A Table 6B. LVDS Output Test Conditions ...

Page 15

IDT5T93GL10 2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Package Outline and Package Dimensions Package Outline - K Suffix for 40 Lead VFQFPN S eating Plan e Ind ex Area View D Chamfer 4x 0.6 x 0.6 ...

Page 16

IDT5T93GL10 06 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Ordering Information Table 8. Ordering Information XX XXXXX IDT Device Type Package IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ Process I NL NLG 5T93GL10 16 -40°C to +85°C (Industrial) Thermally Enhanced Plastic ...

Page 17

IDT5T93GL10 2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Revision History Sheet Rev Table Page T3A, T3B IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II Description of Change Features Section ...

Page 18

IDT5T93GL10 2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Contact Information: www.IDT.com Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT © 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and ...

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