LMH6581VS National Semiconductor, LMH6581VS Datasheet - Page 20

• Manufacturer Part Number: LMH6581VS
• Manufacturer: National Semiconductor

Specifications of LMH6581VS

• Array Configuration: 8x4
• Number Of Arrays: 1
• Screening Level: Industrial
• Pin Count: 48
• Package Type: TQFP
• Power Supply Requirement: Dual
• Lead Free Status / RoHS Status: Not Compliant

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Serial Mode Data Frame (First Two Words)
Off = TRI-STATE
Serial Mode Data Frame (Continued)
ADDRESSED PROGRAMMING MODE
Addressed programming mode makes it possible to change
only one output register at a time. To utilize this mode the
mode pin must be High. All other pins function the same as
in serial programming mode except that the word clocked in
is 5 bits and is directed only at the output specified. In ad-
dressed mode the data format is shown below in the table
titled Addressed Mode Word Format.
Also illustrated is the timing relationships for the digital pins
in the Timing Diagram for Addressed Mode shown below. It
is important to note that all the pin timing relationships are
important, not just the data and clock pins. One example is
that the Chip Select pin (CS) must transition low before the
®
, Bit 0 is first bit clocked into device.
Output 0
Input Address
LSB
0
Output 2
Input Address
LSB
8
1
9
MSB
2
MSB
10
Timing Diagram for Addressed Mode
On = 0
Off = 1
3
On = 0
Off = 1
11
20
Output 1
Input Address
LSB
4
Output 3
Input Address
LSB
12
first rising edge of the clock signal. This allows the internal
timing circuits to synchronize to allow data to be accepted on
the next falling edge. The chip select pin must then transition
high after the final data bit has been clocked in and before
another clock signal positive edge occurs to prevent invalid
data from being clocked into the chip. Also, in addressed
mode is it necessary for the clock signal to make a low to high
transition after the chip select pin has been brought high. If
there is not a low to high transition of the clock after the chip
select pin goes high subsequent data wil not be loaded into
the chip properly. The configure (CFG) pin timing is not criti-
cal, but it does need to be kept low until all data has been
shifted into the crosspoint registers.
LSB
5
13
6
MSB
14
On = 0
Off = 1
7
On = 0
Off = 1
15
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