5962-8953202QA QP SEMICONDUCTOR, 5962-8953202QA Datasheet - Page 29

• Manufacturer Part Number: 5962-8953202QA
• Manufacturer: QP SEMICONDUCTOR

Specifications of 5962-8953202QA

• Lead Free Status / RoHS Status: Not Compliant

DSCC FORM 2234
APR 97
Mnemonic
D0 - D7
CEN
WRN
RDN
A0 – A3
RESET
INTRN
X1/CLK
X2
RxDA
RxDB
DEFENSE SUPPLY CENTER COLUMBUS
MICROCIRCUIT DRAWING
COLUMBUS, OHIO 43218-3990
28
01
X
X
X
X
X
X
X
X
X
X
X
STANDARD
Number of pins:
40
02
X
X
X
X
X
X
X
X
X
X
X
Package
Device:
44
02
X
X
X
X
X
X
X
X
X
X
X
52
02
X
X
X
X
X
X
X
X
X
X
X
TABLE III. Pin descriptions.
For device types 01 and 02.
Type
I/O
O
I
I
I
I
I
I
I
I
Data Bus: Bidirectional three-state data bus used to transfer
commands, data and status between the DUART and the
CPU. D0 is the least significant bit.
Chip Enable: Active low input signal. When low, data
transfers between the CPU and the DUART are enabled on D0
– D7 as controlled by the WRN, RDN, and A0 – A3 inputs.
When high, places the D0 – D7 lines in three-state condition.
Write Strobe: When low and CEN is also low, the contents of
the data bus are loaded into the addressed register. The
transfer occurs on the rising edge of the signal.
Read Strobe: When low and CEN is also low, causes the
contents of the addressed register to be presented on the data
bus. The read cycle begins on the falling edge of RDN.
Address Inputs: Selects the DUART internal registers and
ports for read/write operations.
Reset: A high level clears internal registers (SRA, SRB, IMR,
ISR, OPR, OPCR), puts OP0 – OP7 in the high state, stops
the counter/timer, and puts channels A and B in the inactive
state, with the TxDA and TxDB outputs in the mark (high)
state.
Interrupt Request: Active low, open drain, output which signals
the CPU that one or more of the eight maskable interrupting
conditions are true.
Crystal 1: Crystal or external clock input. A crystal or clock of
the specified limits must be supplied at all times. When a
crystal is used, a capacitor must be connected from this pin to
ground (see figure 4 herein).
Crystal 2: Connection for other side of the crystal. When a
crystal is used, a capacitor must be connected from this pin to
ground (see figure 4 herein).
Channel A Receiver Serial Data Input: The least significant bit
is received first. “Mark” is high, “space” is low.
Channel B Receiver Serial Data Input: The least significant bit
is received first. “Mark” is high, “space” is low.
SIZE
A
Name and function
REVISION LEVEL
C
SHEET
5962-89532
29