82V2048SBB IDT, Integrated Device Technology Inc, 82V2048SBB Datasheet - Page 7

• Manufacturer Part Number: 82V2048SBB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2048SBB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Table-1 Pin Description (Continued)
IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED
MODE0/CODE
MODE2
MODE1
CS/JAS
Name
(Pulled to
(Pulled to
VDDIO/2)
VDDIO/2)
Type
I
I
I
I
TQFP144
11
43
88
87
Pin No.
PBGA160
H12
J11
E2
K2
MODE2: Control Mode Select 2
The signal on this pin determines which control mode is selected to control the device:
Hardware control pins include MODE[2:0], TS[2:0], LP[7:0], CODE, CLKE, JAS and OE.
Serial host Interface pins include CS, SCLK, SDI, SDO and INT.
Parallel host Interface pins include CS, A[4:0], D[7:0], WR/DS, RD/R/W, ALE/AS, INT and RDY/ACK. The
device supports multiple parallel host interface as follows (refer to MODE1 and MODE0 pin descriptions
below for details):
MODE1: Control Mode Select 1
In parallel host mode, the parallel interface operates with separate address bus and data bus when this pin
is low, and operates with multiplexed address and data bus when this pin is high.
In serial host mode or hardware mode, this pin should be grounded.
MODE0: Control Mode Select 0
In parallel host mode, the parallel host interface is configured for Motorola compatible hosts when this pin
is low, or for Intel compatible hosts when this pin is high.
CODE: Line Code Rule Select
In hardware control mode, the B8ZS (for T1 mode)/HDB3 (for E1 mode) encoder/decoder is enabled when
this pin is low, and AMI encoder/decoder is enabled when this pin is high. The selections affect all the
channels.
In serial host mode, this pin should be grounded.
CS: Chip Select (Active Low)
In host mode, this pin is asserted low by the host to enable host interface. A high to low transition must
occur on this pin for each read/write operation and the level must not return to high until the operation is
over.
JAS: Jitter Attenuator Select
In hardware control mode, this pin globally determines the Jitter Attenuator position:
MODE[2:0]
VDDIO/2
Hardware/Host Control Interface
High
JAS
Low
100
101
110
111
VDDIO/2
MODE2
High
Low
7
Jitter Attenuator (JA) Configuration
Non-multiplexed Motorola Mode Interface
Non-multiplexed Intel Mode Interface
JA in transmit path
Multiplexed Motorola Mode Interface
JA in receive path
Multiplexed Intel Mode Interface
JA not used
Description
Host Interface
Parallel Host Interface
Serial Host Interface
Control Interface
Hardware Mode
INDUSTRIAL TEMPERATURE RANGES