LAN91C96-MS Standard Microsystems (SMSC), LAN91C96-MS Datasheet - Page 5

• Manufacturer Part Number: LAN91C96-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN91C96-MS

• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
CHAPTER 12 TIMING DIAGRAMS ........................................................................... 99
CHAPTER 13 LAN91C96 REVISIONS .................................................................... 125
List of Figures
Figure 3.1 - LAN91C96 100 Pin QFP...........................................................................................................................11
Figure 3.2 - LAN91C96 100 Pin TQFP.........................................................................................................................12
Figure 3.3 - LAN91C96 System Block Diagram ...........................................................................................................13
Figure 3.4 – System Diagram for Local Bus with Boot Prom .......................................................................................14
Figure 4.1 - LAN91C96 Internal Block Diagram ...........................................................................................................22
Figure 5.1 – Mapping and Paging vs. Receive and Transmit Area ..............................................................................25
Figure 5.2 – Transmit Queues and Mapping................................................................................................................26
Figure 5.3 – Receive Queues and Mapping.................................................................................................................27
Figure 5.4 - LAN91C96 Internal Block Diagram with Data Path...................................................................................28
Figure 5.5 – Logical Address Generation and Relevant Registers...............................................................................29
Figure 6.1 – Data Frame Format..................................................................................................................................38
Figure 6.2 - LAN91C96 Registers ................................................................................................................................41
Figure 7.1 – Interrupt Structure.....................................................................................................................................61
Figure 8.1 – Interrupt Service Routine .........................................................................................................................70
Figure 8.2 - RX INTR ...................................................................................................................................................71
Figure 8.3 -TX INTR.....................................................................................................................................................72
Figure 8.4 -TXEMPTY INTR ........................................................................................................................................73
Figure 8.5 – Driver Send and Allocate Routines ..........................................................................................................74
Figure 8.6 – Interrupt Generation for Transmit; Receive, MMU ...................................................................................78
FIGURE 9.1 - MMU PACKET NUMBER FLOW AND RELEVANT REGISTERS.........................................................84
FIGURE 10.1 - 64 X 16 SERIAL EEPROM MAP .........................................................................................................91
Figure 12.1 – Card Configuration Registers – Read/Write PCMCIA Mode (A15=1) ....................................................99
Figure 12.2 – Local Bus Consecutive Read Cycles ...................................................................................................100
Figure 12.3 - PCMCIA Consecutive Read Cycles ......................................................................................................101
Figure 12.4 – Local Bus Consecutive Write Cycles....................................................................................................102
Figure 12.5 - PCMCIA Consecutive Write Cycles ......................................................................................................103
Figure 12.6 – Local Bus Consecutive Read and Write Cycles ...................................................................................104
Figure 12.7 – Data Register Special Read Access ....................................................................................................105
Figure 12.8 – Data Register Special Write Access.....................................................................................................106
Figure 12.9 - 8-Bit Mode Register Cycles ..................................................................................................................107
Figure 12.10 - 68000 Read Timing.............................................................................................................................108
Figure 12.11 - 68000 Write Timing.............................................................................................................................109
Figure 12.12 – External ROM Read Access ..............................................................................................................110
Figure 12.13 – Local Bus Register Access When Using Bale ....................................................................................111
Figure 12.14 – External ROM Read Access Using Bale ............................................................................................112
Figure 12.15 - EEPROM Read...................................................................................................................................113
Figure 12.16 - EEPROM Write ...................................................................................................................................114
Figure 12.17 - PCMCIA Attribute Memory Read/Write (A15=0) .................................................................................115
Figure 12.18 – External ENDEC Interface – Start of Transmit ...................................................................................115
Figure 12.19 – External ENDEC Interface – Receive Data ........................................................................................116
Figure 12.20 – Differential Output Signal Timing (10BASE-T and AUI) .....................................................................117
Figure 12.21 – Receive Timing – Start of Frame (AUI and 10BASE-T) .....................................................................118
Figure 12.22 – Receive Timing – End of Frame (AUI and 10BASE-T).......................................................................119
Figure 12.23 – Transmit Timing – End of Frame (AUI and 10BASE-T)......................................................................120
Figure 12.24 – Collision Timing (AUI) ........................................................................................................................121
Figure 12.25 – Memory Read Timing.........................................................................................................................121
Figure 12.26 – Input Clock Timing .............................................................................................................................122
Figure 12.27 – Memory Write Timing .........................................................................................................................122
Figure 12.28 - 100 PIN QFP Package........................................................................................................................123
Figure 12.29 - 100 PIN TQFP Package .....................................................................................................................124
SMSC LAN91C96 5v&3v
Page 5
Revision 1.0 (10-24-08)
DATASHEET