75P42100S83BX IDT, Integrated Device Technology Inc, 75P42100S83BX Datasheet - Page 3

• Manufacturer Part Number: 75P42100S83BX
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 75P42100S83BX

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Signal Descriptions
Network Search Engine 32K x 72 Entries
NSE Request Bus:
NSE Response Bus:
Depth Expansion:
Clock and Initialization:
Command
Index Bus
Chip Enable/ Output Enable
Bus
Advance Burst Address
Clock Phase Enable
Match Acknowledge
Read Acknowledge
Pin Function
Request Data Bus
Device Address
Request Strobe
Write Enable
Clock Input
Lookup Bit
Multi Match
Last SRAM
Last NSE
Output
Output
Match
Match
Reset
Valid
Input
Comparand and
Register Select
Result Register
Lookup Type
Lookup Type
Global Mask
Instruction
Device ID
Address
Select
(Open Drain)
Input/Output
Three State
Three State
Three State
Three State
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Description
care" for maintenance typ e commands (all Reads and Writes).
Global Mask Register groups are b eing accessed. This field is a "don't care" for Read, SRAM No Wait
Read, and Learn Operations.
Index into, and the Comparand Register to use. This field is sampled every input clock cycle. The first
cycle decodes the selected Comparand Register and the second decodes the selected Result Register.
NSE, and to present search data for lookups.
directly to the NSE's ASIC/FPGA. The Index Bus contain the encoded location at which the compare was
active for both SRAM write operations and the Learn command.
being read from the associated external SRAM.
lookup did not result in a hit.
or mo re hits occur in two (or more) segments; or, c) one or more hits occur in multiple devices that are
depth cascaded.
expanded NSE devices in an NSE system.
NSEs that a hit in a higher priority NSE has occurred.
Input line of all lower priority NSE(s).
memory in the NSE. This provides a mechanism to conveniently initialize the NSE memory.
This input signifies a valid input request and signals the start of an NSE operation cycle.
These two fields of the Command bus define the instruction to be performed by the NSE and the lookup
type. The lookup type is selected only for operational type commands (Lookups, Learns) and is a "don't
This field is within the Command bus. During Lookup or Write operations, this field defines which of the
This is a multiplexed field within the Command Bus that specifies both the Result Register to store the
The Request Data Bus is a multiplexed address/data bus used to perform reads (and writes) from (to) the
This bus is used to drive the address of an external SRAM, or feedback Lookup result information
found, the address of the NSE which found the result and the Lookup type.
This signal is driven along with the Index Bus. It is connected to the CE input pin of a ZBT SRAM or to the
OE pin of a PBSRAM.
This signal is driven along with the Index bus. It is used to assert the WE pin of an external SRAM. It is
This signal is sent back when the data is read from the NSE on the Request Data Bus, or when the data
This is signal is sent with the Index. It will be driven low if there was no match, high if a match was found.
This signal is sent with the Index. It will be driven high upon the completion of a lookup, even if the
This signal is sent with the Index. It shall go active when a) multiple hits occur in one segment; or, b) one
These three DC pins are used to define the Device Address for each of the eight possible depth
The Match Input signal is driven by all upstream Match Output signals. This indicates to all down stream
The Match Output signal signifies that a match has occurred in the NSE. The signal is fed into a Match
All inputs and outputs are referenced to the positive edge of this clock.
This signal is used to generate an internal clock at ½ the freque ncy of the input clock.
This pin will force all outputs to a high impedence condition, as well as clearing the NSE enable bit.
This signal will advance an internal address counter to allow for burst writes when writing to the Data/Mask
This pin defines which NSE device will drive the ASIC Feedback signals to the ASIC/FPGA.
This pin defines which NSE device will drive the SRAM control signals CE/OE and WE. It also defaults
this device to driving the Index Bus when there is no ongoing operation preventing the bus from floating.
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Datasheet Brief 75P42100
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