WG82567LM S LAVU Intel, WG82567LM S LAVU Datasheet
WG82567LM S LAVU
Specifications of WG82567LM S LAVU
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WG82567LM S LAVU Summary of contents
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GbE Physical Layer Transceiver (PHY) Datasheet Product Features Reduced power consumption during normal operation and power down modes IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab) conformance Supports ...
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... Intel Corporation (“Intel”). In the event that you do not agree with any of these terms and conditions, do not use or install the Pre-Release Product and promptly return it unused to Intel. ...
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... Power Supply Pins ............................................................................................. 10 3.0 Features .................................................................................................................. 11 3.1 Feature Matrix and Product Information................................................................ 11 3.2 Power Saving Features....................................................................................... 12 ® 3.2.1 Intel Auto Connect Battery Saver (ACBS) ................................................ 12 3.2.2 Link Speed Battery Saver ........................................................................ 12 3.2.3 System Idle Power Saver (SIPS) .............................................................. 13 3.2.4 Low Power Link Up (LPLU) ....................................................................... 13 3.2.5 LAN Disable ........................................................................................... 14 4 ...
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... Initial release (Intel secret) January 2007 0.25 Corrected pin numbers and made minor text corrections (Intel Confidential) Corrected GLAN TX pin numbers; added RSET & DIS_REG1_0 to the signal descriptions; corrected February 2007 0.26 LAN_DISABLE# (active high) to LAN_DISABLE_N (active low); in the Visual Pin Assignment Diagram, pin 37, “ ...
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... The 82567 is a single port GbE Physical Layer Transceiver (PHY) that connects to its Media Access Controller (MAC) through a dedicated interconnect. The 82567 is based on Intel's GbE PHY technology, and supports operation at data rates of 10/100/1000 Mb/s. The physical layer circuitry provides a standard IEEE 802.3 Ethernet interface for 10BASE-T, 100BASE-TX, and 1000BASE-T applications (802 ...
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... Intel® 82567 Gigabit Platform XX82567LF LAN Connect Device Intel® 82567 Gigabit Platform XX82567V LAN Connect Device 1. For more information regarding the differences, please contact your Intel field representative Product Name Description Gigabit LAN for high-end Corporate and Workstation designs ...
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Datasheet—82567 2.0 Signal Descriptions 2.1 Signal Type Definitions The signals are defined as follows in the table below: Type In (I) Out (O) T/s S/st/s O/d A-in A-out 2.2 GLCI Interface Pins Signal Name GLAN_RXP GLAN_RXN ...
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LCI Interface Pins Signal Name JKCLK JRSTSYNC JTXD2 JTXD1 JTXD0 JRXD2 JRXD1 JRXD0 2.4 Miscellaneous Pins Signal Name IEEE_TEST_P 12 IEEE_TEST_N 13 LAN_DISABLE_N 37 RSET 15 RESERVED_NC 51 8 Pin Type LCI/GLCI Clock The clock is driven by the ...
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... Intel ICH9/ICH10 NVM word 17h. LED2 1 O This signal is used for the programmable LED programmed ® through the Intel ICH9/ICH10 NVM word 18h. Pins Type Media Dependent Interface [0] In MDI configuration, MDI_PLUS[0]+/- is used for the transmit pair A and in MDI-X configuration MDI_MINUS[0]+/- is used for the receive pair ...
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JTAG_TRST 35 JTAG_TMS 39 TEST_EN 36 Note: The 82567 uses the JTAG interface to support XOR files for manufacturing test. BSDL is not supported. 2.6 Power Supply Pins Signal Name 3 VCC3_3 VCC1_05 ...
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... Basic manageability includes ASF & DASH support. For firmware and hardware requirements, please refer to Intel® chipset documentation. *** For Platform features, other Intel® component skus may be required. Please refer to the relevant Intel® component (chipset/CPU) documentation for sku requirements. Production information is in the 82567 Specification Update available from Intel on the Intel Business Link ...
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... Mb full duplex/half duplex, then 10 Mb full duplex/half duplex. Note: Intel Auto Connect Battery Saver for the 82567 is only supported if autonegotiation is enabled. If link speed is forced and the network cable is disconnected, the 82567 will not enter ACBS, resulting in higher power consumption than specified in section 4.6. ...
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Datasheet—82567 possible. The Windows NDIS drivers (Windows XP and later), monitor the AC-to-DC transition on the system to make the PHY negotiate to the lowest connection speed supported by the link partner (usually 10 Mb) when the user unplugs the ...
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... ICH9, ICH9M, or ICH10. The GPIO12 needs to configured using ICH soft straps as LAN_PHY_PWR_CTRL (bit [20] of STRP0 register - LAN_PHY_PWR_CTRL/GPIO12 Select (LAN_PHY_PWR_GPIO12_SEL) set to “1.” This can be done with the Intel FIT tool by setting LAN_PHY_PWR_CTRL in ICH STRP0 to native mode (“1”). Please refer to ICH9 EDS Section 22.2.5.1 for more details. ...
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Datasheet—82567 In addition, LAN_PHY_PWR_CTRL can also be used to turn the 3.3 V power off to the 82567 when the PHY is disabled. This will also turn the PHY off when in Sx state and WOL is disabled from the ...
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Voltage, Temperature, and Timing Specifications 4.1 Recommended Operating Conditions Table 2. Recommended Operating Conditions Symbol VCCP VCC1p8 Core/Analog Voltage Range VCC1p0 Core Digital Voltage Range 4.2 DC and AC Characteristics Table 3. DC and AC Characteristics Symbol Parameter High-threshold ...
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Datasheet—82567 4.4 Crystal Specifications Following are the recommended crystal specifications for operation with the 82567. Parameter Name Frequency Vibration mode Cut Operating/Calibration Mode Frequency Tolerance Temperature Tolerance Operating Temperature Non Operating Temperature Equivalent Series Resistance (ESR) Load Capacitance Shunt Capacitance ...
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Figure 3. Crystal Connectivity to the 82567 The current from the 82567 does not change regardless of generating the 1.05 V using the on-die transistor or an external pass transistor. The total current demand remains constant, but the power dissipated ...
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Datasheet—82567 4.5 Oscillator Specifications Table 5. Oscillator Specifications and Timing Requirements Parameter Name Frequency Swing Frequency Tolerance Temperature Stability Operating Temperature Aging Coupling capacitor Calibration mode Oscillator Load Capacitance Shunt Capacitance Series Resistance, Rs Drive Level Insulation Resistance T H_XTAL_IN ...
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Vin = VDD * (C1/(C1 + Cstray)) Vin = 3.3 * (C1/(C1 + Cstray)) This enables load clock oscillators used. If the value should be adjusted by tuning the input clock amplitude ...
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Datasheet—82567 Table 6. Power Consumption–82567 with external Voltage regulator, 1.9V (VCC1P8) State Mode 1000Mbps Active, 90°c [Ta Max 1000Mbps Idle, 90°c [Ta] 1000Mbps Active 1000Mbps Idle 100Mbps Active 100Mbps Idle 10Mbps Active S0 - Typ 10Mbps Idle Cable ...
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Table 7. Power Consumption–82567 with internal Voltage regulator, 1.9V (VCC1P8) State 1000Mbps Active, 90°c [Ta Max 1000Mbps Idle, 90°c [Ta] 1000Mbps Active 1000Mbps Idle 100Mbps Active 100Mbps Idle 10Mbps Active S0 - Typ 10Mbps Idle Cable Disconnect (ACBS) ...
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Datasheet—82567 Table 8. Power Consumption–82567 with external Voltage regulator; 1.8 V State Mode 1000Mbps Active, 90°c [Ta Max 1000Mbps Idle, 90°c [Ta] 1000Mbps Active 1000Mbps Idle 100Mbps Active 100Mbps Idle 10Mbps Active S0 - Typ 10Mbps Idle Cable ...
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Table 9. Power Consumption–82567 with internal Voltage regulator, 1.8 V State 1000Mbps Active, 90 °C [Ta Max 1000Mbps Idle, 90 °C [Ta] 1000Mbps Active 1000Mbps Idle 100Mbps Active 100Mbps Idle 10Mbps Active S0 - Typ 10Mbps Idle Cable ...
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Datasheet—82567 4.7.2 The 1.05 V Rail The 1.05 V power delivery system supports a load of 300 mA. The 1.05 V rail can be supplied in one of three ways: • An external power supply that is not dependent on ...
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Title Input Capacitance Capacitance ESR Ictrl Note: Do not use tantalum capacitors. 4.7.4.3 1.05 Rail Title Rise Time Monotonicity Slope Operational Range Ripple Overshoot Output Capacitance Input Capacitance Capacitance ESR Ictrl 4.7.5 PNP Specifications Title VCBO VCEO IC(max) IC(peak) Ptot ...
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Datasheet—82567 4.7.6 Power Sequencing For proper and safe operation, the power supplies must follow the following rule: VDDO (3.3 V) > AVDD (1 1.9 V) > DVDD (1.05 V) This means that VDDO must start ramping before AVDD ...
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Timing Parameters 4.8.1 Timing Requirements The 82567 requires the following start-up and power state transitions. Table 10. Timing Requirements Parameter T JRST_min Tc2dud Tr2init 4.8.2 Timing Guarantees The 82567 guarantees the following start-up and power state transition related timing ...
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Datasheet—82567 5.0 Package and Pinout Information The physical characteristics of the 82567 are described in this section. The pin number to signal mapping is indicated in 5.1 Package Information The package used for the 82567 is an 56-pin QFN package. ...
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Internal Pull-Up Resistors Table 12 lists the internal pull-up resistors and their functionality in different device states. Each internal pull-up resistor has a nominal value of 5 k, ranging from 2.7 k to 8.6 k Table 12. Internal ...
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Datasheet—82567 5.4 Visual Pin Assignments Pin 1 LED2 1 LED1 2 VCC3_3 3 LED0 4 VCC1_05 5 JTAG_TDO 6 JTAG_TDI 7 8 VCC1_05 XTAL2 9 XTAL1 10 VCC1_8 11 IEEE_TEST_P 12 IEEE_TEST_N 13 VCC1_8 14 Note: VCC1_8 range is 1.71 ...
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Table 13. Pin Mapping Pin Pin Name Pin LED2 29 LED1 ...
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Datasheet—82567 33 ...