HBLXT9785HE.D0 Cortina Systems Inc, HBLXT9785HE.D0 Datasheet - Page 201

• Manufacturer Part Number: HBLXT9785HE.D0
• Manufacturer: Cortina Systems Inc

Specifications of HBLXT9785HE.D0

• Lead Free Status / RoHS Status: Supplier Unconfirmed

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Table 94
Table 95
Cortina Systems
Quick Status Register (Address 17, Hex 11)
Interrupt Enable Register (Address 18, Hex 12)
®
1. R = Read Only, LH = Latching High – cleared when read.
2. The default values are updated on completion of reset and reflect the status or change in status at that
3. The default value is determined by the default value of Register bit 0.12.
4. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
5. Default values are set by the hardware configuration PAUSE pin. The BGA15 package does not have a
1. R/W = Read/Write
2. In 10 Mbps operation, Register bit 18.13 = 1 cannot be used when Register bits 18.15:14 = “11” and in
3. SFD Frame Alignment is applicable to SMII and SS-SMII only.
4. LSHR = Default value is derived from a single device input pin state or a group of device input pin states
5. Default values are set by hardware configuration pins FIFOSEL1 and FIFOSEL0 (see
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
15:14
Bit
2:0
7
6
5
4
3
Bit
time. Cortina recommends that the register status be read on completion of reset.
the pin(s) are latched at startup or hardware reset.
Pause hardware configuration pin. The default for the BGA15 package is 0.
RMII mode, Registers bits 18.15:14 = “11” or “10” cannot be used because the minimum Inter Gap Packet
becomes less than specified in the *IEEE 802.3 specification.
as the pin(s) are latched at startup or hardware reset
FIFO Depth Considerations , on page
2
Name
Auto-Negotiation
Complete
FIFO Error
Polarity
Pause
Error
Reserved
Name
RxFIFO Initial
Fill
Description
0 = Auto-negotiation process is not complete
1 = Auto-negotiation process is complete
0 = No FIFO error occurred
1 = FIFO error occurred (overflow or underflow)
0 = Polarity is not reversed
1 = Polarity is reversed
Note:
0 = The LXT9785/LXT9785E is not Pause capable
1 = The LXT9785/LXT9785E is pause capable
Note:
Note:
0 = No error occurred
1 = Error Occurred (remote fault, RxERCntFUL, FIFO
Note:
Write as 0, ignore on Read.
Description
00 = Reserved
01 = Low, 16 bits
10 = Normal, 32 bits (default)
11 = Jumbo packets, 128 bits
error, jabber, parallel detect fault)
During 100 Mbps operation, this bit is not valid
and may vary. Auto MDIX activity may increase
the variability.
This bit is not affected by Register bit 4.10.
The default for the BGA15 package is 0.
The register is cleared when the registers that
generated the error condition are read.
50).
7.0 Register Definitions
Type
Table 17, Receive
Type
R/W
LH
R
R
R
R
R
R
1
1
Page 201
LSHR
Default
LSHR
Default
0
0
0
0
0
2
4,5
4,5