CY7B933-JIT Cypress Semiconductor Corp, CY7B933-JIT Datasheet - Page 29

CY7B933-JIT

Manufacturer Part Number
CY7B933-JIT
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7B933-JIT

Lead Free Status / RoHS Status
Not Compliant
Document #: 38-02017 Rev. *E
Receiver Switching Characteristics
Switching Waveforms for the CY7B923 HOTLink Transmitter
Notes:
26. The PECL switching threshold is the midpoint between the PECL− V
27. Static alignment is a measure of the alignment of the Receiver sampling point to the center of a bit. Static alignment is measured by sliding one bit edge in 3,000
28. Error Free Window is a measure of the time window between bit centers where a transition may occur without causing a bit sampling error. EFW is measured
t
t
t
t
t
Parameter
CPXH
CPXL
DS
SA
EFW
nominal transitions until a byte error occurs.
over the operating range, input jitter < 50% Dj.
CKW
ENA
D
SC/D,
SVS,
BISTEN
RP
0
–D
REFCLK Clock Pulse HIGH
REFCLK Clock Pulse LOW
Propagation Delay SI to SO (note PECL and TTL
thresholds)
Static Alignment
Error Free Window
7
,
CKW
ENN
D
SC/D,
SVS,
BISTEN
0
–D
7
,
[26]
[13, 27]
[13, 28]
Description
NOTES 16,17
t
CPWL
t
SD
Over the Operating Range (continued)
t
SENP
t
PDF
t
OH
CPWL
, and V
t
HD
t
t
SD
PDR
t
SD
t
VALID DATA
CPWH
OL
specification (approximately V
0.9t
Min.
7B933-155
6.5
6.5
t
t
B
HENP
HD
t
t
CKW
PPWH
Max
100
t
20
CPWH
0.9t
Min.
[7]
6.5
6.5
t
CKW
7B933
B
CC
t
SD
VALID DATA
− 1.35V). The TTL switching threshold is 1.5V.
DISABLED
ENABLED
Max.
100
20
t
HD
0.9t
Min.
6.5
6.5
7B933-400
B
CY7B923
CY7B933
Page 29 of 33
Max.
100
20
Unit
ns
ns
ns
ps
[+] Feedback

Related parts for CY7B933-JIT