ICS1892Y-10 IDT, Integrated Device Technology Inc, ICS1892Y-10 Datasheet - Page 62

• Manufacturer Part Number: ICS1892Y-10
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS1892Y-10

• Lead Free Status / RoHS Status: Supplier Unconfirmed

8.2 Register 0: Control Register
8.2.1 Reset (bit 0.15)
ICS1892, Rev. D, 2/26/01
Table 8-5
of the ICS1892.
•
•
•
Note:
Table 8-5. Control Register (Register 0 [0x00]
† Whenever the PHY address of
‡ As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value
to all Reserved bits.
This bit controls the software reset function. Setting this bit to logic one initiates an ICS1892 software reset
during which all Management Registers are set to their default values and all internal state machines are
set to their idle state. For a detailed description of the software reset process, see
“Software
During reset, the ICS1892 leaves bit 0.15 set to logic one and isolates all STA management register
accesses for 640 ns. However, the reset process is not complete until bit 0.15 (a Self-Clearing bit), is set to
logic zero, which indicates the reset process is terminated.
0.15
0.14
0.13
0.12
0.11
0.10
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Bit
•
•
The Control Register is accessible through the MII Management Interface.
Its operation is independent of the MAC/Repeater Interface configuration.
It is fully compliant with the ISO/IEC Control Register definition.
Is equal to 00000 (binary), the Isolate bit 0.10 is logic one.
Is not equal to 00000, the Isolate bit 0.10 is logic zero.
ICS1892 Data Sheet
Reset
Loopback enable
Data rate select
Auto-Negotiation enable
Low-power mode
Isolate
Auto-Negotiation restart
Duplex mode
Collision test
IEEE reserved
IEEE reserved
IEEE reserved
IEEE reserved
IEEE reserved
IEEE reserved
IEEE reserved
For an explanation of acronyms used in
lists the bits for the Control Register, a 16-bit register used to establish the basic operating modes
Reset”.
Definition
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
Table
Normal power mode
No effect
Always 0
Always 0
Always 0
Always 0
Always 0
Always 0
Always 0
No effect
Disable Loopback mode
10 Mbps operation
Disable Auto-Negotiation Enable Auto-Negotiation
No effect
Half-duplex operation
No effect
8-16:
When Bit = 0
62
Table
8-5, see
ICS1892 enters Reset
mode
Enable Loopback mode
100 Mbps operation
Low-power mode
Isolate ICS1892 from MII
Restart Auto-Negotiation
Full-duplex operation
Enable collision test
N/A
N/A
N/A
N/A
N/A
N/A
N/A
When Bit = 1
Chapter 1, “Abbreviations and
Chapter 8 Management Register Set
cess
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Section 5.1.2.3,
Ac-
RO
RO
RO
RO
RO
RO
RO
SC
SC
February 26, 2001
SF
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Acronyms”.
fault
0/1†
De-
0‡
0‡
0‡
0‡
0‡
0‡
0‡
0
0
1
1
0
0
0
0
0/4†
Hex
3
0
0