DS92LX2122SQE National Semiconductor, DS92LX2122SQE Datasheet
DS92LX2122SQE
Specifications of DS92LX2122SQE
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DS92LX2122SQE Summary of contents
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... The Serializer is offered in a 40-pin lead in LLP and Deseri- alizer is offered in a 48-pin LLP packages. Typical Application Diagram TRI-STATE® registered trademark of National Semiconductor Corporation. © 2011 National Semiconductor Corporation DS92LX2121 / DS92LX2122 Features ■ ...
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Block Diagrams www.national.com FIGURE 1. Block Diagram FIGURE 2. Application Block Diagram 2 30125128 30125129 ...
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... LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch DS92LX2121SQ 40-pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch DS92LX2121SQX 40-pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch DS92LX2122SQE 48-pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch DS92LX2122SQ 48-pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch DS92LX2122SQX 48-pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch DS92LX2121 Pin Diagram Serializer - DS92LX2121 — ...
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DS92LX2121 Serializer Pin Descriptions Pin Name Pin No. LVCMOS PARALLEL INTERFACE DIN[20: 40, Inputs, LVCMOS w/ 39, 38, 37, 36, 35, 33, 32, 30, 29, 28, 27, 26, 25, 24, 23 PCLK 6 Input, LVCMOS ...
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DS92LX2122 Pin Diagram Deserializer - DS92LX2122 — Top View 5 30125120 www.national.com ...
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DS92LX2122 Deserializer Pin Descriptions Pin Name Pin No. LVCMOS PARALLEL INTERFACE ROUT[20: 10, 11, Outputs, LVCMOS 12, 13, 14, 15, 16, 18, 19, 21, 22, 23, 24, 25, 26, 27, 28 PCLK 4 Output, LVCMOS General ...
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Pin Name Pin No. RIN+ 41 Input/Output, CML RIN- 42 Input/Output, CML POWER AND GROUND VDDSSCG 3 Digital Power VDDOR1/2/3 29, 20, 7 Digital Power VDDD 17 Digital Power VDDR 36 Analog Power VDDCML 40 Analog Power VDDPLL 45 Analog ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( V ) DD1V8 Supply Voltage (V ) DD3V3 LVCMOS Input Voltage (V ) −0.3V to +(V DD1V8 LVCMOS Input Voltage (V ) −0.3V to +(V DD3V3 LVCMOS Output Voltage (V ...
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Symbol Parameter I Output Short Circuit Current OS I TRI-STATE® Output Current RPWDNB = 0V, OZ CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT Output Differential Voltage OD Output Differential Voltage ΔV OD Unbalance Output Differential Offset V OS Voltage ...
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Symbol Parameter Deserializer (Rx) I VDDn Supply Current DDR (includes load current) I Deserializer (Rx) DDIOR VDDIO Supply Current (includes load current) I Deserializer (Rx) Supply DDRZ Current Power-down I DDIORZ Recommended Serializer Timing for PCLK Over recommended operating supply ...
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Symbol Parameter Peak-to-peak Serializer t JINT Output Jitter Serializer Jitter Transfer λ STXBW Function -3 dB Bandwidth Serializer Jitter Transfer δ STX Function (Peaking Serializer Jitter Transfer δ Function (Peaking STXf Frequency) Deserializer Switching Characteristics Over recommended operating supply and ...
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Bi-Directional Control Bus AC Timing Specifications (SCL, SDA Compliant (Figure 3) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter RECOMMENDED INPUT TIMING REQUIREMENTS () f SCL Clock Frequency SCL f SCL Low Period LOW ...
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Bi-Directional Control Bus DC Characteristics (SCL, SDA Symbol Parameter V Input High Level IH V Input Low Level Voltage IL V Input Hysteresis HY I TRI-STATE® Output OZ Current I Input Current IN C Input Pin Capacitance IN ...
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AC Timing Diagrams and Test Circuits FIGURE 5. Serializer CML Output Load and Transition Times www.national.com FIGURE 4. “Worst Case” Test Pattern 14 30125152 30125146 30125147 ...
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FIGURE 6. Serializer VOD DC Diagram FIGURE 7. Low-Voltage Differential VTH/VTL Definition Diagram FIGURE 8. Serializer Input Clock Transition Times 15 30125148 30125130 30125116 www.national.com 30125134 ...
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FIGURE 9. Serializer Setup/Hold Times FIGURE 10. Serializer Data Lock Time FIGURE 11. Serializer Delay FIGURE 12. Deserializer Data Lock Time 16 30125149 30125132 30125150 30125113 ...
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FIGURE 13. Deserializer LVCMOS Output Load and Transition Times FIGURE 14. Deserializer Delay FIGURE 15. Deserializer Output Setup/Hold Times FIGURE 16. Spread Spectrum Clock Output Profile 17 30125114 30125111 30125131 30125135 www.national.com ...
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FIGURE 17. Typical Serializer Jitter Transfer Function Curve at 43 MHz FIGURE 18. Typical Deserializer Input Jitter Tolerance Curve at 43 MHz www.national.com 30125162 30125159 18 ...
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TABLE 1. DS92LX2121 Control Registers Addr Name Bits Field (Hex) 7:1 DEVICE Device SER ID 7:3 RESERVED 2 STANDBY 1 Reset DIGITAL 1 RESET0 0 DIGITAL RESET1 2 Reserved 7:0 RESERVED Reserved 7:6 ...
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Addr Name Bits Field (Hex) B Reserved 7:0 RESERVED Reserved 7:3 RESERVED PCLK Detect 2 PCLK DETECT C Reserved 1 RESERVED Cable Link 0 LINK DETECT Detect Status D Reserved 7:0 RESERVED E Reserved 7:0 RESERVED F Reserved 7:0 RESERVED ...
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TABLE 2. DS92LX2122 Control Registers Addr Name Bits (Hex) 7:1 DEVICE Device DES ID 7:3 RESERVED 2 REM_WAKEUP 1 Reset 1 DIGITALRESET0 0 DIGITALRESET1 Reserved 7:6 RESERVED Auto Clock 5 AUTO_CLOCK OSS Select ...
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Addr Name Bits (Hex) Reserved 7:6 RESERVED VDDIO VDDIO Control 5 CONTROL VDDIO Mode 4 VDDIO MODE Pass-Through 3 THROUGH Auto ACK 2 AUTO ACK Reserved 1 RESERVED RRFB 0 RRFB 4 EQ Control ...
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Addr Name Bits (Hex) 7:1 SER DEV ID 7 SER ID 0 RESERVED ID[0] Index 7:1 ID[0] INDEX 8 0 RESERVED 7:1 ID[1] INDEX 9 ID[1] Index 0 RESERVED 7:1 ID[2] INDEX A ID[2] Index 0 RESERVED 7:1 ID[3] INDEX ...
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Addr Name Bits (Hex) 22 Reserved 7:0 RESERVED GPCR[7] GPCR[6] GPCR[5] General Purpose GPCR[4] 23 7:00 Control Reg GPCR[3] GPCR[2] GPCR[1] GPCR[0] Reserved 7:1 RESERVED BIST 0 BIST_EN 24 25 BIST_ERR 7:0 BIST_ERR REM_WAKEUP_ 7:6 Remote Wake EN 26 Enable ...
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Functional Description The DS92LX2121 / DS92LX2122 Channel Link III chipset is intended for camera applications. The Serializer/ Deserializer chipset operates from a 10 MHz to 50 MHz pixel clock fre- quency. The DS92LX2121 transforms a 21-bit wide parallel LVCMOS data ...
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FIGURE 20. Write Byte FIGURE 21. Read Byte FIGURE 22. Basic Operation FIGURE 23. START and STOP Conditions 26 30125160 30125110 30125141 30125142 ...
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SLAVE CLOCK STRETCHING In order to communicate and synchronize with remote de- vices on the bus through the bi-directional control channel, slave clock stretching must be supported by the I controller/host device. The chipset utilizes bus clock ...
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CAMERA MODE OPERATION In Camera mode transactions originate from the Deseri- alizer from the host controller. The I Deserializer will detect if a transaction is intended for the Se- rializer or a slave at the Serializer. Commands ...
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GENERAL PURPOSE I/O (GPIO) The DS92LX2121 / DS92LX2122 has GPO and 4 GPI on the Serializer and Deserializer respectively. The GPI/GPO maximum switching rate kHz for communication between Deserializer GPI to Serializer GPO. ...
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Step 1: Place the Deserializer in BIST Mode. Serializer and Deserializer power supply must be supplied. Set the Serializer M/S pin to LOW and the Deserializer M/S pin to HIGH. Enable the AT SPEED BIST mode on the De- Freq ...
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Step 3: Stop at SPEED BIST by turning off BIST mode in the Deserializer to determine Pass/Fail. To end BIST, the system must pull BISTEN pin of the Dese- rializer LOW. The BIST duration is fully defined by the BIS- ...
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LOCK pin and confirm LOCK = H before performing any I communication across the link. For Remote Wakeup to function properly: • The chipset needs to be configured in Camera mode: Serializer M and Deserializer M ...
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Applications Information AC COUPLING The SER/DES supports only AC-coupled interconnects through an integrated DC balanced decoding scheme. Exter- For high-speed Channel Link III transmissions, the smallest available package should be used for the AC coupling ca- pacitor. This will help ...
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FIGURE 31. DS92LX2121 Typical Connection Diagram 34 30125155 ...
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Figure 32 shows a typical connection of the DS92LX2122 Deserializer. FIGURE 32. DS92LX2122 Typical Connection Diagram 35 30125156 www.national.com ...
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TRANSMISSION MEDIA The Ser/Des chipset is intended to be used over a wide variety of balanced cables depending on distance and signal quality requirements. The Ser/Des employ internal termination pro- viding a clean signaling environment. The interconnect for Channel Link ...
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Physical Dimensions inches (millimeters) unless otherwise noted DS92LX2121 Serializer NS Package Number SQA40A DS92LX2122 Deserializer NS Package Number SQA48A 37 www.national.com ...
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