XC6SLX25-2FTG256C Xilinx Inc, XC6SLX25-2FTG256C Datasheet - Page 49

• Manufacturer Part Number: XC6SLX25-2FTG256C
• Description: FPGA, SPARTAN-6 LX, 24K, 256FTGBGA
• Manufacturer: Xilinx Inc
• Series: Spartan® 6 LXr

Specifications of XC6SLX25-2FTG256C

• No. Of Logic Blocks: 3758
• No. Of Macrocells: 24051
• Family Type: Spartan-6
• No. Of Speed Grades: 2
• Total Ram Bits: 958464
• No. Of I/o's: 186
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Package / Case: 256-BGA
• Mounting Type: Surface Mount
• Voltage - Supply: 1 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Number Of I /o: 186
• Number Of Logic Elements/cells: 24051
• Core Supply Voltage Range: 1.14V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PLL Switching Characteristics
Table 50: PLL Specification
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Notes:
1.
2.
3.
4.
5.
6.
F
F
F
F
F
F
F
T
T
T
T
F
F
F
T
RST
F
F
T
INMAX
INMIN
INJITTER
INDUTY
VCOMIN
VCOMAX
BANDWIDTH
STAPHAOFFSET
OUTJITTER
OUTDUTY
LOCKMAX
OUTMAX
OUTMAX
OUTMIN
EXTFDVAR
PFDMAX
PFDMIN
FBDELAY
LXT devices are not available with a -1L speed grade.
Values for this parameter are available in the Clocking Wizard.
The PLL does not filter typical spread spectrum input clocks because they are usually far below the bandwidth filter frequencies.
Includes global clock buffer.
Calculated as F
When using CLK_FEEDBACK = CLKOUT0 with BUFIO2 feedback, the feedback frequency will be higher than the phase frequency detector
frequency. F
MINPULSE
Symbol
(5)
PFDMAX
VCO
Maximum Input Clock Frequency from I/O Clock
Maximum Input Clock Frequency from Global Clock
Minimum Input Clock Frequency
Maximum Input Clock Period Jitter
Allowable Input Duty Cycle: 19—199 MHz
Allowable Input Duty Cycle: 200—299 MHz
Allowable Input Duty Cycle: > 300 MHz
Minimum PLL VCO Frequency
Maximum PLL VCO Frequency
Low PLL Bandwidth at Typical
High PLL Bandwidth at Typical
Static Phase Offset of the PLL Outputs
PLL Output Jitter
PLL Output Clock Duty Cycle Precision
PLL Maximum Lock Time
PLL Maximum Output Frequency for BUFGMUX
PLL Maximum Output Frequency for BUFPLL
PLL Minimum Output Frequency
External Clock Feedback Variation
Minimum Reset Pulse Width
Maximum Frequency at the Phase Frequency Detector LX Family
Minimum Frequency at the Phase Frequency Detector
Maximum Delay in the Feedback Path
/128 assuming output duty cycle is 50%.
= F
CLKFB
/ CLKFBOUT_MULT
(3)
Description
(3)
(3)
(5)
www.xilinx.com
(4)
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
LX Family
LXT Family
LX Family
LXT Family
LX Family
LXT Family
All
All
All
All
LX Family
LXT Family
LX Family
LXT Family
All
All
All
All
All
All
LX Family
LXT Family
LX Family
LXT Family
All
All
All
LXT Family
LX Family
LXT Family
All
Device
(1)
3.125
1080
1080
1080
1080
0.12
0.15
< 20% of clock input period or 1 ns Max
540
540
400
400
400
400
100
400
400
500
500
<20% of clock input period or 1 ns Max
19
19
19
19
-3
1
4
5
3 ns Max or one CLKIN cycle
3.125
Speed Grade
1050
1050
1050
1050
0.12
0.15
-3N
525
525
400
400
400
400
100
400
400
500
500
19
19
19
19
1
4
5
25/75
35/65
45/55
Note 2
3.125
1000
1000
0.12
0.20
450
450
375
375
400
400
375
375
950
950
400
400
100
19
19
19
19
-2
1
4
5
3.125
1000
0.15
0.25
300
N/A
250
N/A
N/A
400
N/A
N/A
100
250
N/A
500
N/A
300
N/A
N/A
-1L
19
19
1
4
5
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
µs
ns
%
%
%
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