PIC12LF1840-E/P Microchip Technology, PIC12LF1840-E/P Datasheet - Page 291

• Manufacturer Part Number: PIC12LF1840-E/P
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Nano
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 12Fr

Specifications of PIC12LF1840-E/P

• Processor Series: PIC12F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 7 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Core Processor: RISC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 5
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

FIGURE 26-12:
TABLE 26-8:
 2011 Microchip Technology Inc.
BAUDCON
INTCON
PIE1
PIR1
RCREG
RCSTA
SPBRGL
SPBRGH
TXSTA
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Reception.
(SCKP = 0)
(SCKP = 1)
(Interrupt)
Note:
TX/CK pin
TX/CK pin
CREN bit
SREN bit
bit SREN
RCIF bit
RCREG
Name
RX/DT
Write to
Read
pin
*
Page provides register information.
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
‘0’
TMR1GIE
TMR1GIF
ABDOVF
CSRC
SPEN
Bit 7
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
GIE
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
bit 0
RCIDL
ADIE
PEIE
ADIF
Bit 6
RX9
TX9
bit 1
TMR0IE
SREN
TXEN
RCIE
RCIF
Bit 5
—
EUSART Receive Data Register
bit 2
Preliminary
CREN
SCKP
SYNC
INTE
Bit 4
TXIE
TXIF
BRG<15:8>
BRG<7:0>
bit 3
ADDEN
SENDB
BRG16
SSPIE
SSPIF
IOCIE
Bit 3
bit 4
TMR0IF
CCP1IE
CCP1IF
BRGH
FERR
Bit 2
—
bit 5
PIC12(L)F1840
TMR2IE
TMR2IF
OERR
TRMT
WUE
Bit 1
INTF
bit 6
TMR1IE
TMR1IF
ABDEN
bit 7
IOCIF
RX9D
TX9D
Bit 0
DS41441B-page 291
Register
on Page
272*
279*
279*
278
277
276
83
84
86
‘0’