PIC16F1826-E/SS Microchip Technology, PIC16F1826-E/SS Datasheet - Page 5

• Manufacturer Part Number: PIC16F1826-E/SS
• Description: 3.5 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core 20
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1826-E/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5. Module: ADC
5.1 Analog-to-Digital Conversion
1.
2.
FIGURE 1:
 2011 Microchip Technology Inc.
See the ADC Clock Period (T
section of the device data sheet.
F
T
T
An ADC conversion may not complete under these
conditions:
When F
clock source used for the ADC converter.
The ADC is operating from its dedicated internal
FRC oscillator and the device is not in Sleep
mode (any F
When this occurs, the ADC Interrupt Flag (ADIF)
does not get set, the GO/DONE bit does not get
cleared, and the conversion result does not get
loaded into the ADRESH and ADRESL result
registers.
Work around
In
required to complete the full conversion. Each T
cycle consists of 8 T
provided to stop the A/D conversion after 86
instruction cycles and terminate the conversion at
the correct time as shown in the figure above.
CY
AD
OSC
Figure
= 4/32 MHz = 125 nsec
= 1 µsec, ADCS = F
= 32 MHz
Method 1: Select the system clock, F
Method 2: Select
4 T
OSC
8 T
1 T
1, 88 instruction cycles (T
CY
CY
is greater than 8 MHz and it is the
OSC
AD
INSTRUCTION CYCLE DELAY CALCULATION EXAMPLE
the ADC clock source and reduce
the F
less
conversions.
oscillator as the ADC conversion
clock source and perform all
conversions with the device in
Sleep.
frequency).
CY
OSC
when
OSC
periods. A fixed delay is
the
frequency to 8 MHz or
/32
AD
) vs. Device Operating Frequencies table, in the Analog-to-Digital Converter
performing
dedicated
88 T
11 T
84 T
CY
CY
AD
) will be
CY
OSC
ADC
FRC
, as
AD
PIC16(L)F1826/1827
Method 3: This method is provided if the
application cannot use Sleep
mode and requires continuous
operation at frequencies above 8
MHz. This method requires early
termination of an ADC conver-
sion. Provide a fixed time delay in
software to stop the A-to-D
conversion manually, after all 10
bits are converted, but before the
conversion
automatically. The conversion is
stopped by clearing the GO/
DONE bit in software. The GO/
DONE bit must be cleared during
the last ½ T
conversion
completed automatically. Refer to
Figure 1
Stop the A/D conversion
between 10.5 and 11 T
cycles.
See the Analog-to-Digital
Conversion
figure in the Analog-to-
Digital Converter chapter of
the device data sheet.
for details.
AD
would
cycle, before the
T
DS80485G-page 5
would
AD
Cycles
complete
AD
have