PIC18LF8628T-I/PT Microchip Technology, PIC18LF8628T-I/PT Datasheet - Page 32

• Manufacturer Part Number: PIC18LF8628T-I/PT
• Description: PIC18 With 96KB Flash, 4KB RAM, 1024 DataEE, 12-bit ADC 80 TQFP 12x12x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF8628T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 96KB (48K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18LF8628T-I/PTTR

PIC18F872X FAMILY
TABLE 5-3:
DS39643C-page 32
WAIT
BW
ABW<1:0>
PM<1:0>
MCLRE
LPT1OSC
ECCPMX
CCP2MX
DEBUG
XINST
BBSIZ<1:0>
LVP
STVREN
CP7
CP6
Note 1:
Bit Name
2:
(1)
The BBSIZ<1:0> bits cannot be changed once any of the following code-protect bits are enabled: CPB or CP0, WRTB
or WRT0, EBTRB or EBTR0.
Available on PIC18F8XXX devices only.
PIC18F872X FAMILY CONFIGURATION BIT DESCRIPTIONS (CONTINUED)
Configuration
CONFIG3H
CONFIG3H
CONFIG3H
CONFIG3H
CONFIG3L
CONFIG3L
CONFIG3L
CONFIG3L
CONFIG4L
CONFIG4L
CONFIG4L
CONFIG4L
CONFIG4L
CONFIG5L
CONFIG5L
Words
External Bus Wait Enable bit
1 = Wait selections from MEMCON.WAIT<1:0> are unavailable and the device will not wait
0 = Wait programmed by MEMCON.WAIT<1:0>
Data Bus Width Select bit
1 = 16-Bit External Bus mode
0 = 8-Bit External Bus mode
Address Bus Width Select bits
11 = 20-bit address bus
10 = 16-bit address bus
01 = 12-bit address bus
00 = 8-bit address bus
Processor Data Memory Mode Select bits
11 = Microcontroller mode
10 = Microprocessor mode
01 = Microprocessor with Boot Block mode
00 = Extended Microcontroller mode
MCLR Pin Enable bit
1 = MCLR pin enabled, RE3 input pin disabled
0 = RE3 input pin enabled, MCLR pin disabled
Low-Power Timer1 Oscillator Enable bit
1 = Timer1 configured for low-power operation
0 = Timer1 configured for higher power operation
ECCP Mux bit
1 = Enhanced CCP1/3 (P1B/P1C/P3B/P3C) are multiplexed on to RE6, RE5, RE4 and
0 = Enhanced CCP1/3 (P1B/P1C/P3B/P3C) are multiplexed on to RH7, RH6, RH5 and
CCP2 MUX bit
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3 in Extended Microcontroller,
Background Debugger Enable bit
1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
Boot Block Size Select bits
11 = 4K words (8 Kbytes) Boot Block
10 = 4K words (8 Kbytes) Boot Block
01 = 2K words (4 Kbytes) Boot Block
00 = 1K words (2 Kbytes) Boot Block
Low-Voltage Programming Enable bit
1 = Low-Voltage Programming enabled, RB5 is the PGM pin
0 = Low-Voltage Programming disabled, RB5 is an I/O pin
Stack Overflow/Underflow Reset Enable bit
1 = Reset on stack overflow/underflow enabled
0 = Reset on stack overflow/underflow disabled
Code Protection bits (Block 7 code memory area)
1 = Block 7 is not code-protected
0 = Block 7 is code-protected
Code Protection bits (Block 6 code memory area)
1 = Block 6 is not code-protected
0 = Block 6 is code-protected
RE3, respectively
RH4, respectively
Microprocessor or Microprocessor with Boot Block mode
(2)
Description
© 2009 Microchip Technology Inc.