W40S11-23G Cypress Semiconductor Corp, W40S11-23G Datasheet - Page 2

• Manufacturer Part Number: W40S11-23G
• Manufacturer: Cypress Semiconductor Corp

Specifications of W40S11-23G

• Number Of Outputs: 13
• Operating Supply Voltage (max): 3.47V
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (min): 3.14V
• Mounting: Surface Mount
• Pin Count: 28
• Operating Supply Voltage (typ): 3.3V
• Package Type: SOIC
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

Pin Definitions
Functional Description
Output Drivers
The W40S11-23 output buffers are CMOS type which deliver
a rail-to-rail (GND to V
Table 1. Byte Writing Sequence
SDRAM0:12
BUF_IN
SDATA
SCLOCK
VDD
GND
Sequence
Pin Name
Byte
10
1
2
3
4
5
6
7
8
9
Slave Address
Command
Code
Byte Count
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
2, 3, 6, 7, 10,
1, 5, 13, 20,
4, 8, 16, 17,
11, 18, 19,
22, 23, 26,
Byte Name
27, 12
24, 28
21, 25
Pin
No.
14
15
DD
9
) output voltage swing into a nominal
Type
Pin
I/O
O
G
P
11010010
Don’t Care
Don’t Care
Refer to Table 2
Don’t Care
I
I
Bit Sequence
SDRAM Outputs: Provides buffered copy of BUF_IN. The propagation delay from a
rising input edge to a rising output edge is 1 to 5 ns. All outputs are skew controlled to
within ± 250 ps of each other.
Clock Input: This clock input has an input threshold voltage of 1.5V (typ).
SMBus Data Input: Data should be presented to this input as described in the SMBus
section of this data sheet. Internal 250-k pull-up resistor.
SMBus Clock Input: The SMBus data clock should be presented to this input as
described in the SMBus section of this data sheet. Internal 250-k pull-up resistor.
Power Connection: Power supply for core logic and output buffers. Connected to 3.3V
supply.
Ground Connection: Connect all ground pins to the common system ground plane.
Commands the W40S11-23 to accept the bits in Data Bytes 0–6 for in-
ternal register configuration. Since other devices may exist on the same
common serial data bus, it is necessary to have a specific slave address
for each potential receiver. The slave receiver address for the W40S11-23
is 11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
Unused by the W40S11-23, bit values are ignored (Don’t Care). This byte
must be included in the data write sequence to maintain proper byte
allocation. The Command Code Byte is part of the standard serial com-
munication protocol and may be used when writing to another addressed
slave receiver on the serial data bus.
Unused by the W40S11-23, bit values are ignored (Don’t Care). This byte
must be included in the data write sequence to maintain proper byte
allocation. The Byte Count Byte is part of the standard serial communi-
cation protocol and may be used when writing to another addressed slave
receiver on the serial data bus.
The data bits in these bytes set internal W40S11-23 registers that control
device operation. The data bits are only accepted when the Address Byte
bit sequence is 11010010, as noted above. For description of bit control
functions refer to Table 2.
Refer to Cypress Frequency Timing Generators.
2
capacitive load. Thus output signaling is both TTL and CMOS
level compatible. Nominal output buffer impedance is 15 .
Operation
Data is written to the W40S11-23 in ten bytes of eight bits
each. Bytes are written in the order shown in Table 1.
Pin Description
Byte Description
W40S11-23
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