FAGD1654348BA Intel, FAGD1654348BA Datasheet - Page 2

• Manufacturer Part Number: FAGD1654348BA
• Manufacturer: Intel

Specifications of FAGD1654348BA

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Not Compliant

Functional Details
The main application of the GD16543 is
as a receiver for:
u
u
It integrates:
u
u
u
u
into a Phase Locked Loop (PLL) - based
clock and data recovery circuit followed
by a 1:4 demultiplexer with differential
ECL data and clock outputs.
VCO
The VCO is a low noise LC-type differen-
tial oscillator with a tuning range from 2.2
to 2.7 GHz. Tuning is done by applying a
voltage to the VCTL pin.
Lock Detect Circuit
The lock detect circuit continuously moni-
tors the difference between the reference
clock and the divided VCO clock. If the
reference clock and the divided VCO fre-
quency differs by more than 500 ppm (or
2000 ppm, selectable), it switches the
PFD into the PLL in order to pull the VCO
back inside the lock-in range. This mode
is called the acquisition mode.
The PFD is used to ensure predictable
lock up conditions for the GD16543 by
locking the VCO to an external reference
clock source. It is only used during acqui-
sition and pulls the VCO into the lock
range where the Bang-Bang phase de-
tector is capable of acquiring lock. The
PFD is made with digital set/reset cells
giving it a true phase and frequency
characteristic.
Once the VCO is inside the lock-range
the lock-detection circuit switches the
Bang-Bang phase detector into the PLL
in order to lock to the data signal. This
mode is called CDR mode.
For the purpose of stand alone applica-
tions the GD16543 has been equipped
with a crystal oscillator for a series reso-
nance, fundamental mode crystal. A
crystal for use at 2.488 GHz is also avail-
able. When not used with a crystal, the
REFXI input can be used as a standard
ECL input.
The reference clock input, REFXI, to the
PFD is at 1/64 of the data rate.
Data Sheet Rev.: 07
SDH STM-16
SONET OC-48 optical communica-
tion systems.
a Voltage Controlled Oscillator (VCO)
a Lock Detect Circuit
a Frequency Detector (PFD)
a Bang-Bang Phase Detector
Bang-Bang Phase Detector
The Bang-Bang phase detector is used
in CDR mode as a true digital type de-
tector, producing a binary output. It sam-
ples the incoming data twice each bit
period: once in the transition of the (pre-
vious) bit period and once in the middle
of the bit period. When a transition
value of the sample in the transition be-
tween the bits will show whether the
VCO clock leads or lags the data. Hence
the PLL is controlled by the bit transition
point, thereby ensuring that data is sam-
pled in the middle of the eye, once the
system is in CDR mode. The external
loop filter components control the chara-
cteristics of the PLL.
The binary output of either the PFD or
the Bang-Bang phase detector (depend-
ing of the mode of the lock-detection cir-
cuit) is fed to a charge pump capable of
sinking or sourcing current or tristating.
The output of the charge pump is filtered
through the loop filter and controls the
tune-voltage of the VCO.
As a result of the continuous monitoring
lock-detect circuit the VCO frequency
never deviates more than 500 ppm
(2000 ppm) from the reference clock be-
fore the PLL is considered to be ’Out of
Lock’. Hence the acquisition time is pre-
dictable and short and the output clock
CKOUT is always kept within the
500 ppm (2000 ppm) limits, ensuring
safe clocking of down stream circuitry.
The LOCK Signal
The status of the lock-detection circuit is
given by the LOCK signal. In CDR mode
LOCK is steady high. In acquisition mode
LOCK is alternating indicating the con-
tinuous shifts between the Bang-Bang
Detector (high) and the PFD (low).
The LOCK output may be used to gener-
ate Loss Of Signal (LOS). The time for
LOCK to assert is predictable and short,
equal to the time to go into lock, but the
time for LOCK to de-assert must be con-
sidered. When the line is down (i.e. no in-
formation received) the optical receiver
circuit may produce random noise. It is
possible that this random noise will keep
the GD16543 within the 500 ppm
(2000 ppm) range of the line frequency,
hence LOCK will remain asserted for a
non-deterministic time. This may be pre-
vented by injecting a small current at the
loop filter node, which actively pulls the
PLL out of the lock range when the out-
put of the phase detector acts randomly.
occurs between 2 consecutive bits - the
GD16543
The negligible penalty paid is a static
phase error on the sampling time in the
decision gate. However, due to the na-
ture of the phase detector the error will
be small (few degrees), forcing the loop
to be at one edge of the error-function
shaped transfer characteristic of the de-
tector.
Inputs
The input amplifier (pin SIPI / SINI) is de-
signed as a limiting amplifier with a sen-
sitivity better than 20 mV (differential).
The inputs may be either AC or DC cou-
pled. In both cases input termination is
made through pins SIPO / SINO. If the
inputs are AC coupled the amplifier fea-
tures an internal offset cancelling DC
feedback. Notice that the offset cancella-
tion will only work when the input is dif-
ferential and AC-coupled as shown in the
Figures at page 3.
Following the CDR block the data is 1:4
demultiplexed and output together with a
622 MHz clock. The data and clock out-
puts are differential ECL outputs that
should be terminated via 50 W to -2 V.
Package
The GD16543 is provided in either a
48 lead power enhanced TQFP or in a
40 pin Multi Layer Ceramic package with
internal 50 W transmission lines.
Page 2 of 9