ADV7304AKST Analog Devices Inc, ADV7304AKST Datasheet - Page 58

• Manufacturer Part Number: ADV7304AKST
• Manufacturer: Analog Devices Inc

Specifications of ADV7304AKST

• Number Of Dac's: 6
• Adc/dac Resolution: 14b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

ADV7304A/ADV7305A
Appendix E
SD TIMING MODES
[Subaddress 4Ah]
Mode 0 (CCIR-656): Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7304A/ADV7305A is controlled by the start active video
(SAV) and end active video (EAV) time codes in the pixel data. All
Mode 0 (CCIR-656): Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7304A/ADV7305A generates H, V, and F signals
required for the SAV and EAV time codes in the CCIR-656
standard. The H Bit is output on the S_HSYNC pin, the V Bit
is output on the S_BLANK pin, and the F Bit is output on the
S_VSYNC pin.
H
V
F
H
V
F
522
260
DISPLAY
DISPLAY
523
261
NTSC/PAL M SYSTEM
(625 LINES/50Hz)
(525 LINES/60Hz)
524
262
INPUT PIXELS
PAL SYSTEM
ANALOG
525
263
VIDEO
264
1
ODD FIELD
Y
END OF ACTIVE
VIDEO LINE
265
C
r
EVEN FIELD
2
Y
F
F
4 CLOCK
4 CLOCK
EAV CODE
Figure 95. SD Master Mode 0, NTSC
266
EVEN FIELD
0
0
3
0
0
Figure 94. SD Slave Mode 0
X
Y
ODD FIELD
267
8
0
4
1
0
8
0
268
5
1
0
VERTICAL BLANK
–58–
269
VERTICAL BLANK
ANCILLARY DATA
6
0
0
268 CLOCK
280 CLOCK
F
F
timing information is transmitted using a 4-byte synchronization
pattern. A synchronization pattern is sent immediately before and
after each line during active picture and retrace. S_VSYNC,
S_HSYNC, and S_BLANK (if not used) pins should be tied high
during this mode. Blank output is available.
(HANC)
F
F
270
7
A
B
A
B
A
B
271
8
8
0
272
9
1
0
8
0
1
0
SAV CODE
273
10
4 CLOCK
F
F
4 CLOCK
START OF ACTIVE
0
0
VIDEO LINE
0
0
274
11
X
Y
C
b
Y C
1440 CLOCK
1440 CLOCK
r
Y
C
b
283
20
Y
C
r
Y
284
C
b
21
285
DISPLAY
DISPLAY
22
REV. A