LM4548VHNOPB National Semiconductor, LM4548VHNOPB Datasheet - Page 13

• Manufacturer Part Number: LM4548VHNOPB
• Manufacturer: National Semiconductor

Specifications of LM4548VHNOPB

• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3/4.2V
• Single Supply Voltage (max): 5.5V
• Package Type: LQFP
• Lead Free Status / RoHS Status: Compliant

Application Information
SDATA_OUT Slot 1: Control Address
Slot 1 is used both to write to the LM4548 registers as well
as read back a register’s current value. The MSB of Slot 1
(bit 19) signifies whether the current control operation is a
read or a write. Bits 18 through 12 are used to specify the
register address of the read or write operation. The least sig-
nificant twelve bits are reserved and should be stuffed with
zeros by the AC’97 controller.
SDATA_OUT Slot 2: Control Data
Slot 2 is used to transmit 16 bit control data to the LM4548 in
the event that the current operation is a write operation. The
least significant four bits should be stuffed with zeros by the
AC ’97 controller. If the current operation is a register read,
the entire slot, bits 19 through 0 should be stuffed with zeros.
AC Link Input Frame: SDATA_IN (input to controller,
output from LM4548)
The audio input frame (input to the AC ’97 Digital Controller)
contains status and PCM data from the LM4548 control reg-
isters and stereo ADC. The Tag slot, slot 0, contains 16 bits
that tell the AC ’97 Digital Controller whether the LM4548 is
ready and the validity of data from certain device subsec-
tions.
A new audio input frame is signaled with a low to high tran-
sition of SYNC. SYNC is synchronous to the rising edge of
BIT_CLK. On the next rising edge of BIT_CLK, the LM4548
drives SDATA_IN with the first bit of slot 0. The Digital Con-
troller samples SDATA_IN on the falling edge of BIT_CLK.
The LM4548 will continue outputting the SDATA_IN stream
on each successive rising edge of BIT_CLK. The LM4548
outputs data MSB first, in a MSB justified format. All reserved
bits and slots are stuffed with 0 ’s by the LM4548.
18:12
Bits
11:0
Bit
11
19
Description
Description
Read/Write
PCM Data
Reserved
Playback
Register
Control
Right
1 = Right PCM Data is
Identifies the Control
1 = Read, 0 = Write
Comment
Comment
Set to 0
Register
(Continued)
valid.
FIGURE 6. AC Link Audio Input Frame
13
SDATA_OUT Slot 3: PCM Playback Left Channel
Slot 3 is a 20 bit field used to transmit data intended for the
left DAC on the LM4548. Any unused bits should be padded
with zeros. The LM4548 DAC’s have 18 bit resolution and
thus will use the first 18 bits of the 20 bit PCM stream.
SDATA_OUT Slot 4: PCM Playback Right Channel
Slot 4 is a 20 bit field used to transmit data intended for the
right DAC on the LM4548. Any unused bits should be pad-
ded with zeros. The LM4548 DAC’s have 18 bit resolution
and thus will use the first 18 bits of the 20 bit PCM stream.
SDATA_OUT Slots 5-12: Reserved
Set these SDATA_OUT slots to 0 as they are not currently
implemented and are reserved for future use.
SDATA_IN Slot 0: Codec Status Bits
The first bit of SDATA_IN Slot 0 (bit 15) indicates when the
Codec is ready. The digital controller must probe further to
see which other subsections are ready.
19:4
19:0
19:0
Bits
Bits
Bits
3:0
Register Write
Data for Right
Data for Left
Description
Description
Description
PCM Audio
PCM Audio
Reserved
Control
Data
DAC
DAC
Set unused bits to 0
Set unused bits to 0
Set bits to 0 if read
Comment
Comment
Comment
Set to 0
operation
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