UDA1343TT NXP Semiconductors, UDA1343TT Datasheet - Page 7

• Manufacturer Part Number: UDA1343TT
• Manufacturer: NXP Semiconductors

Specifications of UDA1343TT

• Single Supply Voltage (typ): 3V
• Single Supply Voltage (min): 2.4V
• Single Supply Voltage (max): 3.6V
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
FUNCTIONAL DESCRIPTION
The UDA1343TT accommodates slave mode only, this
means that in all applications the system devices must
provide the system clock and the serial audio clock
signals.
The system clock must be locked in frequency to the digital
interface input signals.
The BCK clock can be up to 128f
BCK frequency f
frequency f
Important: the WS edge MUST fall on the negative edge
of the BCK at all times for correct operation of the digital
I/O data interface.
Note: the sampling frequency range is from 8 to 110 kHz,
however for the 512f
from 8 to 55 kHz.
2001 Jul 25
handbook, halfpage
Economy audio CODEC with features
V DDA(ADC)
V SSA(ADC)
L3CLOCK
WS
L3MODE
OVERFL
SYSCLK
V ADCN
V ADCP
V ref(A)
TEST1
V DDD
V SSD
or less: f
VINR
VINL
BCK
Fig.2 Pin configuration.
10
11
12
13
14
1
2
3
4
5
6
7
8
9
is 128 times the Word Select (WS)
s
clock mode the sampling range is
BCK
UDA1343TT
= < 128
MGL887
s
, or in other words the
19
18
17
16
15
28
27
26
25
24
23
22
21
20
f
WS
V ref(D)
V SSO
VOUTL
V DDO
VOUTR
V DDA(DAC)
V SSA(DAC)
TEST2
RESET
DATAI
DATAO
WS
BCK
L3DATA
.
7
Reset
Pin 20 is a reset pin (active HIGH), which resets the
internal digital core of the IC and also resets all feature
values of the L3 interface to their default settings as given
in Tables 8 and 9.
Since the RESET pin is a pull-down pad with
Schmitt-trigger, a Power-On Reset (POR) function can be
made by connecting this pin to the digital power supply via
a capacitor.
Note: care must be taken that during the HIGH period of
the reset signal it is best to have at least 8 SYSCLK clock
cycles to properly reset the device.
Analog-to-Digital Converter (ADC)
The stereo ADC of the UDA1343TT consists of two
5th-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The oversampling ratio is 64.
Analog front-end
The overall system gain is proportional to V
input level is defined as that which gives a 1 dB
Full-Scale (FS) digital output (relative to the full-scale
swing).
The analog front-end is equipped with a Programmable
Gain Amplifier (PGA) which can be controlled via the L3
interface. The control range is from 0 dB to 24 dB gain in
3 dB steps independant for left and right.
In applications in which a 2 V (RMS) input signal is used,
a 12 k resistor must be connected in series with the input
of the ADC. This makes a voltage divider with the internal
ADC resistor and makes sure only 1 V (RMS) maximum is
input to the IC. Using this application for a 2 V (RMS) input
signal, the switch must be set to 0 dB. When a 1 V (RMS)
input signal is input to the ADC in the same application, the
gain switch of the PGA must be set to 6 dB via the L3
interface.
An overview of the maximum input voltages allowed
against the presence of an external resistor and the setting
of the gain switch is given in Table 1.
UDA1343TT
Product specification
DDA
. The 0 dB