92HD87B2X5NDGXTBX IDT, Integrated Device Technology Inc, 92HD87B2X5NDGXTBX Datasheet - Page 62

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92HD87B2X5NDGXTBX

Manufacturer Part Number
92HD87B2X5NDGXTBX
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of 92HD87B2X5NDGXTBX

Lead Free Status / RoHS Status
Compliant
IDT PROPRIETARY / IDT
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
92HD87
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
Field Name
Control0
Field Name
Rsvd
W2
W1
W0
Reg
Reg
Get
Get
Set
Set
8.3.14. AFG (NID = 01h): GPIOWakeEn
8.3.15. AFG (NID = 01h): GPIOUnsol
Byte 4 (Bits 31:24)
Byte 4 (Bits 31:24)
CONFIDENTIAL
Bits
0
Direction control for GPIO0: 0 = GPIO is configured as input; 1 = GPIO is con-
figured as output
Bits
31:3
Reserved.
2
Wake enable for GPIO2: 0 = wake-up event is disabled; 1 = When HD Audio
link is powered down (RST# is asserted), a wake-up event will trigger a Status
Change Request event on the link.
1
Wake enable for GPIO1: 0 = wake-up event is disabled; 1 = When HD Audio
link is powered down (RST# is asserted), a wake-up event will trigger a Status
Change Request event on the link.
0
Wake enable for GPIO0: 0 = wake-up event is disabled; 1 = When HD Audio
link is powered down (RST# is asserted), a wake-up event will trigger a Status
Change Request event on the link.
Byte 3 (Bits 23:16)
Byte 3 (Bits 23:16)
R/W
RW
R/W
R
RW
RW
RW
F1800h
F1900h
Default
0h
Default
00000000h
0h
0h
0h
62
Byte 2 (Bits 15:8)
Byte 2 (Bits 15:8)
Reset
POR - DAFG - ULR
Reset
N/A (Hard-coded)
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
92HD87
Byte 1 (Bits 7:0)
Byte 1 (Bits 7:0)
718h
719h
PC AUDIO
V 0.95 10/10

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