JL198SGA National Semiconductor, JL198SGA Datasheet - Page 15

• Manufacturer Part Number: JL198SGA
• Manufacturer: National Semiconductor

Specifications of JL198SGA

• Number Of Sample And Hold Elements: 1
• Power Supply Requirement: Dual
• Single Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Not Compliant

Typical Applications
Definition of Terms
Hold Step: The voltage step at the output of the sample and
hold when switching from sample mode to hold mode with a
steady (dc) analog input voltage. Logic swing is 5V.
Acquisition Time: The time required to acquire a new ana-
log input voltage with an output step of 10V. Note that
acquisition time is not just the time required for the output to
settle, but also includes the time required for all internal
nodes to settle so that the output assumes the proper value
when switched to the hold mode.
Gain Error: The ratio of output voltage swing to input volt-
age swing in the sample mode expressed as a per cent
difference.
Differential Hold
(Continued)
20128157
15
**Adjust for amplitude
Hold Settling Time: The time required for the output to
settle within 1 mV of final value after the “hold” logic com-
mand.
Dynamic Sampling Error: The error introduced into the
held output due to a changing analog input at the time the
hold command is given. Error is expressed in mV with a
given hold capacitor value and input slew rate. Note that this
error term occurs even for long sample times.
Aperture Time: The delay required between “Hold” com-
mand and an input analog transition, so that the transition
does not affect the held output.
Capacitor Hysteresis Compensation
20128156
www.national.com