MC33912G5AC Freescale, MC33912G5AC Datasheet - Page 44

• Manufacturer Part Number: MC33912G5AC
• Manufacturer: Freescale

Specifications of MC33912G5AC

• Turn Off Delay Time: 10us
• Number Of Drivers: 4
• Operating Temperature (min): -40C
• Operating Temperature (max): 125C
• Operating Temperature Classification: Automotive
• Lead Free Status / RoHS Status: Compliant

Timing Control Register - TIMCR
sense and Forced Wake-up periods. Writing to the Timing
Control Register (TIMCR) will also return the Watchdog
Status Register (WDSR).
CS/WD - Cyclic Sense or Watchdog Prescaler Select
to, the Cyclic Sense/Forced Wake-up prescaler or the
Watchdog prescaler.
WDx - Watchdog Prescaler
prescaler and therefore selects the watchdog period in
accordance with
windowing watchdog is active.
Table 24. watchdog Prescaler
CYSTx - Cyclic Sense Period Prescaler Select
cyclic sensing together with the bit CYSX8 in the
Configuration Register (CFR) (see page 45).
44
33912
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
WD2
This register allows to configure the watchdog, the cyclic
This write-only bit selects which prescaler is being written
1 = Cyclic Sense/Forced Wake-up Prescaler selected
0 = Watchdog Prescaler select
This write-only bits selects the divider for the watchdog
This write-only bits selects the interval for the wake-up
Table 23. Timing Control Register - $A
0
0
0
0
1
1
1
1
Condition
Reset
Value
Reset
Write
WD1
0
0
1
1
0
0
1
1
CS/WD
Table
C3
-
-
WD0
0
1
0
1
0
1
0
1
24. This configuration is valid only if
CYST2
WD2
C2
0
Prescaler Divider
CYST1
WD1
POR
C1
0
10
12
14
1
2
4
6
8
CYST0
WD0
C0
0
enabled when entering in Stop or Sleep mode. Otherwise, a
timed wake-up is performed after the period shown in
Table
Table 25. Cyclic Sense and Force Wake up Interval
Watchdog Status Register - WDSR
is also returned when writing to the TIMCR.
WDTO - Watchdog Timeout
either a watchdog timeout or by an attempt to clear the
Watchdog within the window closed.
(TIMCR) will clear the WDTO bit.
Notes
CYSX8
71.
72.
This option is only active if one of the high side switches is
This register returns the Watchdog status information and
This read-only bit signals the last reset was caused by
Any access to this register or the Timing Control Register
1 = Last reset caused by watchdog timeout
0 = None
X
0
0
0
0
0
0
0
1
1
1
1
1
1
1
25.
(71)
bit CYSX8 is located in Configuration Register (CFR)
No Cyclic Sense and no Force Wake-up available.
Table 26. Watchdog Status Register - $A/$B
Read
CYST2
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
WDTO
S3
CYST1
Analog Integrated Circuit Device Data
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
WDERR
S2
CYST0
Freescale Semiconductor
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
WDOFF
S1
No cyclic sense
WDWO
1120 ms
Interval
S0
100 ms
120 ms
140 ms
160 ms
320 ms
480 ms
640 ms
800 ms
960 ms
20 ms
40 ms
60 ms
80 ms
(72)