LTC1702ACGN#TR-SMI Linear Technology, LTC1702ACGN#TR-SMI Datasheet - Page 6

• Manufacturer Part Number: LTC1702ACGN#TR-SMI
• Manufacturer: Linear Technology

Specifications of LTC1702ACGN#TR-SMI

• Lead Free Status / RoHS Status: Not Compliant

BLOCK
LTC1702A
PIN
FB1 (Pin 12): Controller 1 Feedback Input. FB1 should be
connected through a resistor network to V
output voltage. The loop compensation network for con-
troller 1 also connects to FB1.
V
except the output drivers are powered from this pin. V
should be connected to a low noise power supply voltage
between 3V and 7V and should be bypassed to SGND with
at least a 1µF capacitor in close proximity to the LTC1702A.
FB2 (Pin 14): Controller 2 Feedback Input. See FB1.
COMP2 (Pin 15): Controller 2 Loop Compensation. See
COMP1.
RUN/SS2 (Pin 16): Controller 2 Run/Soft-start. See RUN/
SS1.
FAULT (Pin 17): Output Overvoltage Fault (Latched). The
FAULT pin is an open-drain output with an internal 10µA
pull-up. If either regulated output voltage rises more than
15% above its programmed value for more than 25µs, the
FAULT output will go high and the entire LTC1702A will be
disabled. When FAULT is high, both BG pins will go high,
6
CC
U
(Pin 13): Power Supply Input. All internal circuits
FUNCTIONS
U
DIAGRAM
U
RUN/SS1,2
COMP1,2
I
MAX1,2
W
10µA
V
CC
550mV
550kHz
OSC
3.5µA
I
LIM
THIS CONTROLLER
SHUTDOWN TO
800mV
OUT1
1V
90% DUTY CYCLE
START
+
SOFT
P-P
FB
CONTROLLER
–
OTHER
FROM
to set the
760mV
PGOOD
CC
BURST
LOGIC
920mV
SHUTDOWN TO
ENTIRE CHIP
turning on the bottom MOSFET switches and pulling down
the high output voltage. The LTC1702A will remain latched
in this state until the power is cycled. When FAULT mode
is active, the FAULT pin will be pulled up with an internal
10µA current source. Tying FAULT directly to PGND will
disable latched FAULT mode and will allow the LTC1702A
to resume normal operation when the overvoltage fault is
removed.
PGOOD2 (Pin 18): Controller 2 Power Good. See PGOOD1.
PGND (Pin 19): Power Ground. The BG n drivers return to
this pin. Connect PGND to a high current ground node in
close proximity to the sources of external MOSFETs, QB1
and QB2, and the V
SW2 (Pin 20): Controller 2 Switching Node. See SW1.
TG2 (Pin 21): Controller 2 Top Gate Drive. See TG1.
BG2 (Pin 22): Controller 2 Bottom Gate Drive. See BG1.
BOOST2 (Pin 23): Controller 2 Top Gate Driver Supply.
See BOOST1.
I
MAX2
FLT
FCB
DELAY
DELAY
100µs
25µs
(Pin 24): Controller 2 Current Limit Set. See I
DRIVE
LOGIC
CONTROLLER
OTHER
FROM
DIS
PV
CC
IN
and V
OUT
1702A BD
BOOST1,2
TG1,2
SW1,2
BG1,2
PGND
SGND
PGOOD1,2
FAULT
FB1,2
bypass capacitors.
MAX1
1702afa
.