LTC1753CSW#TRM Linear Technology, LTC1753CSW#TRM Datasheet - Page 13

• Manufacturer Part Number: LTC1753CSW#TRM
• Manufacturer: Linear Technology

Specifications of LTC1753CSW#TRM

• Lead Free Status / RoHS Status: Not Compliant

APPLICATIO S I FOR ATIO
mounted next to the external MOSFET which is expected
to run the hottest –– often the high-side device, Q1. Elec-
trically, the thermistor should form a voltage divider with
another resistor, R1, connected to V
should be connected to OUTEN (see Figure 6). As the
temperature increases, the OUTEN pin voltage is reduced.
Under normal operating conditions, the OUTEN pin should
stay above 1.7V and all circuits will function normally. If
the temperature gets abnormally high, the OUTEN pin
voltage will eventually drop below 1.7V, the LTC1753
disables both FET drivers. If OUTEN decreases below
1.2V, the LTC1753 enters shutdown mode. To activate any
of these three modes, the OUTEN voltage must drop below
the respective threshold for longer than 30 s.
Clock Synchronization
The internal oscillator can be synchronized to an external
clock by applying the external clocking signal to the
OUTEN pin. The synchronizing range extends from the
initial operating frequency up to 500kHz. If the external
frequency is much higher than the natural free-running
frequency, the peak-to-peak sawtooth amplitude within
the LTC1753 will decrease. Since the loop gain is inversely
proportional to the amplitude of the sawtooth, the com-
pensation network may need to be adjusted slightly. Note
that the temperature sensing circuitry does not operate
when external synchronization is used.
THERMAL PROXIMITY
NTC THERMISTOR
MOUNT IN CLOSE
Figure 6. OUTEN Pin as a Thermistor Input
TO Q1
R2
V
CC
U
R1
OUTEN
LTC1753
U
G2
G1
W
CC
V
IN
Q1
Q2
. Their midpoint
L
O
U
+
C
1753 F06
OUT
V
OUT
MOSFET Gate Drive
Power for the internal MOSFET drivers is supplied by
PV
by at least one power MOSFET V
operation. For a typical application, PV
nected to a 12V power supply.
If the OUTEN pin is low, G1 and G2 are both held low to
prevent output voltage undershoot. As V
power up from a 0V condition, an internal undervoltage
lockout circuit prevents G1 and G2 from going high until
V
ground potential, the SS is forced to ground potential
internally. SS clamps the COMP pin low and prevents the
drivers from turning on. On power-up or recovery from
thermal shutdown, the drivers are designed such that G2
is held low until G1 first goes high.
Power MOSFETs
Two N-channel power MOSFETs are required for most
LTC1753 circuits. Logic level MOSFETs should be used
and they should be selected based on on-resistance and
GATE threshold voltage considerations. R
be chosen based on input and output voltage, allowable
power dissipation and maximum required output current.
GATE threshold voltages for logic level MOSFETs are
lower than standard MOSFETs. A MOSFET whose R
is rated at V
level MOSFET GATE threshold voltage. Using standard
MOSFETs instead of logic level MOSFETs can cause start-
up problems, especially if PV
pump scheme. In a typical LTC1753 buck converter circuit
the average inductor current is equal to the output load
current. This current is always flowing through either Q1
or Q2 with the power dissipation split up according to the
duty cycle:
CC
CC
DC Q
DC Q
reaches about 3.5V. If V
. This supply must be above the input supply voltage
1
2
GS
V
1
V
OUT
IN
= 4.5V does not necessarily have a logic
V
V
OUT
IN
V
IN
CC
CC
V
powers up while PV
IN
V
is derived from a charge
OUT
GS(ON)
CC
LTC1753
should be con-
DS(ON)
CC
for efficient
and PV
13
should
CC
DS(ON)
is at
1753fa
CC