USBUF01P6 STMicroelectronics, USBUF01P6 Datasheet - Page 5
USBUF01P6
Manufacturer Part Number
USBUF01P6
Description
IC EMI FLTR/LINE TERM SOT-666
Manufacturer
STMicroelectronics
Series
IPAD™r
Datasheet
1.USBUF01P6.pdf
(9 pages)
Specifications of USBUF01P6
Filter Type
Signal Line
Mounting Type
Surface Mount
Termination Style
Surface Mount (SMD,SMT)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Inductance
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-3282-2
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
USBUF01P6
Manufacturer:
ST
Quantity:
20 000
USBUF01P6
2.1.2
ESD protection
In addition to the requirements of termination and EMC compatibility, computing devices are
required to be tested for ESD susceptibility. This test is described in IEC 61000-4-2 and is
already in place in Europe. This test requires that a device tolerates ESD events and
remains operational without user intervention.
The USBUF01P6 is particularly optimized to perform ESD protection. ESD protection is
based on the use of device which clamps at:
This protection function is split into 2 stages. As shown in
clamped by the first stage S1 and then its remaining overvoltage is applied to the second
stage through the resistor R
Figure 6.
Figure 7.
To have a good approximation of the remaining voltages at both V
we give the typical dynamical resistance value R
hypothesis: R
The calculation done for V
and R
V
Vinput
Voutput
CL
ESD Surge
=
V
V
d
output
input
V
V
=
= 2
PP
BR
=
R
---------------------------------------------- -
R
--------------------------------------------------------- -
+
g
= 55.48 V
= 10.36 V
t
R
USBUF01P6 ESD clamping behavior
Measurement board
t
V
(typ.) gives:
>R
d
V
BR
BR
R
I
d
PP
, R
+
g
Rg
+
R
R
R
g
d
t
>R
d
V
Vinput
d
g
and R
g
V
= 8 kV, R
t
Rd
. Such a configuration makes the output voltage very low.
BR
S1
Doc ID 9883 Rev 7
Discharge
load
SURGE
15kV
ESD
Air
>R
Vinput
g
USBUF01P6
= 330
d
, gives these formulas:
Rt
Voutput
Vin
TEST BOARD
(IEC 61000-4-2 standard), V
d
. Taking into account the following
Vout
S2
Rd
V
BR
Figure 6.
input
The ESD strikes are
Technical information
and V
protected
Device
to be
Rload
BR
output
= 7 V (typ.)
stages,
5/9