MT48LC8M16A2P-7E:G Micron Technology Inc, MT48LC8M16A2P-7E:G Datasheet - Page 29

• Manufacturer Part Number: MT48LC8M16A2P-7E:G
• Description: IC, SDRAM 128MB, SMD, 48LC8, TSOP54
• Manufacturer: Micron Technology Inc
• Type: SDRAMr
• Series: -r

Specifications of MT48LC8M16A2P-7E:G

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 165mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Access Time: RoHS Compliant
• Memory Case Style: TSOP
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Operating Temperature Max: 70°C
• Operating Temperature Min: 0°C
• Package / Case: TSOP
• Memory Type: SDRAM
• Memory Configuration: 4 BLK (2M X 16)
• Interface Type: LVTTL
• Rohs Compliant: Yes
• Format - Memory: RAM
• Memory Size: 128M (8Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / RoHS Status: Compliant
• Lead Free Status / RoHS Status: Compliant

Figure 15:
Figure 16:
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
READ-to-WRITE
READ-to-WRITE with Extra Clock Cycle
Notes:
Notes:
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 15
shows the case where the clock frequency allows for bus contention to be avoided
without adding a NOP cycle, and Figure 16 shows the case where the additional NOP is
needed.
COMMAND
1. CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE com-
COMMAND
1. CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE com-
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE
command to the same bank (provided that auto precharge was not activated), and a full-
page burst may be truncated with a PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles before the clock edge at which the last
ADDRESS
ADDRESS
mand may be to any bank. If a burst of 1 is used, then DQM is not required.
mand may be to any bank.
DQM
DQM
CLK
CLK
DQ
DQ
BANK,
COL n
T0
T0
BANK,
READ
COL n
READ
TRANSITIONING DATA
T1
T1
NOP
NOP
29
T2
T2
TRANSITIONING DATA
NOP
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
T3
NOP
NOP
D
OUT
t HZ
t HZ
D
OUT
t CK
n
n
DON’T CARE
T4
T4
BANK,
COL b
WRITE
NOP
D
IN
b
t
128Mb: x4, x8, x16 SDRAM
DS
DON’T CARE
T5
BANK,
COL b
WRITE
D
IN
b
t
©1999 Micron Technology, Inc. All rights reserved.
DS
Operations