IS45S16800E-7CTNA2 ISSI, Integrated Silicon Solution Inc, IS45S16800E-7CTNA2 Datasheet - Page 24

• Manufacturer Part Number: IS45S16800E-7CTNA2
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS45S16800E-7CTNA2

• Organization: 16Mx8
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 6.5/5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 130mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

REGISTER command and will retain the stored information
IS45S81600E, IS45S16800E
REGISTER DEFINITION
Mode Register
The mode register is used to define the specific mode
of operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency,
an operating mode and a write burst mode, as shown in
MODE REGISTER DEFINITION.
The mode register is programmed via the LOAD MODE
until it is programmed again or the device loses power.
MODE REGISTER DEFINITION
24
BA1 BA0 A11 A10
Reserved
Write Burst Mode
(1)
M9
0
1
A9
Mode
Programmed Burst Length
Single Location Access
Operating Mode
A8
M8 M7
— —
0
0
A7
Defined
M6-M0
—
Latency Mode
A6
M6 M5 M4
0
0
0
0
1
1
1
1
Mode
Standard Operation
All Other States Reserved
0
0
1
1
0
0
1
1
A5
0
1
0
1
0
1
0
1
Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst (sequential or interleaved), M4- M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10 and
M11 are reserved for future use.
The mode register must be loaded when all banks are
idle, and the controller must wait the specified time before
initiating the subsequent operation. V iolating either of these
requirements will result in unspecified operation.
A4
Burst Type
Integrated Silicon Solution, Inc. — www.issi.com
CAS Latency
M3
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
A3
2
3
Interleaved
Sequential
1. To ensure compatibility with future devices,
A2
Burst Length
Type
should program BA1, BA0, A11, A10 = "0"
M2 M1 M0
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
A0
Address Bus
Mode Register (Mx)
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page
M3=0
1
2
4
8
Reserved
M3=1
1
2
4
8
11/15/2010
Rev. C