MT49H32M18BM-33:A Micron Technology Inc, MT49H32M18BM-33:A Datasheet - Page 38

• Manufacturer Part Number: MT49H32M18BM-33:A
• Manufacturer: Micron Technology Inc
• Type: RLDRAMr

Specifications of MT49H32M18BM-33:A

• Organization: 32Mx18
• Address Bus: 24b
• Operating Supply Voltage (typ): 1.8V
• Package Type: uBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

WRITE
Figure 14:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN
WRITE Command
Write accesses are initiated with a WRITE command, as shown in Figure 14. The address
needs to be provided during the WRITE command.
During WRITE commands, data will be registered at both edges of DK according to the
programmed burst length (BL). The RLDRAM operates with a WRITE latency (WL) that
is one cycle longer than the programmed READ latency (RL + 1), with the first valid data
registered at the first rising DK edge WL cycles after the WRITE command.
Any WRITE burst may be followed by a subsequent READ command (assuming
met). To avoid external data bus contention, at least one NOP command is needed
between the WRITE and READ commands. Figure 21 on page 46 and Figure 22 on
page 47 illustrate the timing requirements for a WRITE followed by a READ where one
and two intermediary NOPs are required, respectively.
Setup and hold times for incoming DQ relative to the DK edges are specified as
t
hold times for the DM signal are also
ADDRESS
ADDRESS
DH. The input data is masked if the corresponding DM signal is HIGH. The setup and
BANK
WE#
REF#
CK#
CS#
CK
576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II
DON’T CARE
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A
38
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DS and
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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DH.
©2004 Micron Technology, Inc. All rights reserved.
Commands
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