MT46H32M32LFCM-75:A Micron Technology Inc, MT46H32M32LFCM-75:A Datasheet - Page 56

• Manufacturer Part Number: MT46H32M32LFCM-75:A
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H32M32LFCM-75:A

• Organization: 32Mx32
• Density: 1Gb
• Address Bus: 13b
• Access Time (max): 6.5/6ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 120mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Bank/Row Activation
PDF: 09005aef82ce3074
1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN
Before any READ or WRITE commands can be issued to a bank within the device, a row
in that bank must be opened. This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated (see Figure 9 (page 34)). After a row is
opened with the ACTIVE command, a READ or WRITE command can be issued to that
row, subject to the
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been precharged. The minimum time interval between
successive ACTIVE commands to the same bank is defined by
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row access overhead. The mini-
mum time interval between successive ACTIVE commands to different banks is defined
by
t
RRD.
t
RCD specification.
56
1Gb: x16, x32 Mobile LPDDR SDRAM
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Bank/Row Activation
© 2007 Micron Technology, Inc. All rights reserved.
t
RC.